eCPRI Intel® FPGA IP User Guide

ID 683685
Date 6/21/2024
Document Table of Contents

5.2.1. Reset Control and Initialization Flows

Figure 21. eCPRI IP Core Reset Logic

Three reset ports of the eCPRI IP assert together to fully reset the eCPRI IP. The deassertion of these three signals can happen together or the IP can just deassert rst_csr_n signal follows by rst_tx_n and rst_rx_n signals depending on use case.

You should perform reset before beginning IP core operation. Alternatively, you can trigger reset after you reconfigure the eCPRI IP during run time.

Reset Length Requirement

You need to assert reset signals for additional ten cycles after tx_lanes_stable and rx_pcs_ready signals are asserted to ensure the Ethernet MAC clocks are stable and run at designated speed. The avst_sink_ready, and mac_sink_ready signals are asserted when the IP core exists from reset successfully and ready to accept client data.