Intel® Stratix® 10 GX FPGA Development Kit User Guide

Download PDF
ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab Board Information System MAX Control JTAG Chain 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

6.3.2. The System Info Tab

The System Info tab shows the board's current configuration. The tab displays the contents of the MAX® V registers, the JTAG chain, the board's MAC address, and other details stored on the board.

Figure 21. The System Info tab

The following sections describe the controls of the System info tab

Board Information

The Board Information control displays static information about your board:
  • Board Name: Indicates the official name of the board given by BTS
  • Board P/N: Indicates the part number of the board
  • Serial Number: Indicates the serial number of the board
  • Board Revision: Indicates the revision of the board
  • MAC: Indicates MAC Address of the board

System MAX Control

MAX Ver: Indicates the version of MAX® V code currently running on the board.

The MAX® V code resides in the <package dir>\examples\max5 directory. Newer revisions of this code may be available on the Intel® Stratix® 10 GX FPGA Development kit link on the Intel® website.

The MAX® V register control allows you to view and change the current MAX® V register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 39.  MAX V Registers
MAX V Register Values Description
Configure Resets the system and reloads the FPGA with a design from the flash memory based on other MAX® V register values.
PSO Sets the MAX® V PSO register.
PSR Sets the MAX® V PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA configuration.
PSS Displays the MAX® V PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.

JTAG Chain

The JTAG chain shows all the devices currently in the JTAG chain.

Note: When set to 1, switch SW6.2 (MAX BYPASS) includes the MAX® V DEVICE in the JTAG chain. When set to 0, the MAX® V device is removed from the JTAG chain. System MAX and FPGA should all be present in the JTAG chain when running BTS GUI.
Level Two Title