Intel® Stratix® 10 GX FPGA Development Kit User Guide

ID 683674
Date 4/02/2020
Document Table of Contents

6.3.2. The System Info Tab

The System Info tab shows the board's current configuration. The tab displays the contents of the MAX® V registers, the JTAG chain, the board's MAC address, and other details stored on the board.

Figure 21. The System Info tab

The following sections describe the controls of the System info tab

Board Information

The Board Information control displays static information about your board:
  • Board Name: Indicates the official name of the board given by BTS
  • Board P/N: Indicates the part number of the board
  • Serial Number: Indicates the serial number of the board
  • Board Revision: Indicates the revision of the board
  • MAC: Indicates MAC Address of the board

System MAX Control

MAX Ver: Indicates the version of MAX® V code currently running on the board.

The MAX® V code resides in the <package dir>\examples\max5 directory. Newer revisions of this code may be available on the Intel® Stratix® 10 GX FPGA Development kit link on the Intel® website.

The MAX® V register control allows you to view and change the current MAX® V register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 39.  MAX V Registers
MAX V Register Values Description
Configure Resets the system and reloads the FPGA with a design from the flash memory based on other MAX® V register values.
PSO Sets the MAX® V PSO register.
PSR Sets the MAX® V PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA configuration.
PSS Displays the MAX® V PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.

JTAG Chain

The JTAG chain shows all the devices currently in the JTAG chain.

Note: When set to 1, switch SW6.2 (MAX BYPASS) includes the MAX® V DEVICE in the JTAG chain. When set to 0, the MAX® V device is removed from the JTAG chain. System MAX and FPGA should all be present in the JTAG chain when running BTS GUI.