Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 12/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 GX FPGA Development Kit User Guide
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel FPGA Download Cable II Driver
2.1. Installing Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 GX FPGA Development Kit User Guide

B. Document Revision History for the Stratix® 10 GX FPGA Development Kit User Guide

Document Version Changes
2025.12.05
  • Updated document per latest branding standards.
  • Made editorial edits throughout the document.
2020.04.02 Added Smart VID Setting
2019.09.20
Updated:
  • Updated Table: PCI Express Pin Assignments, Schematic Signal Names and Functions in PCI Express
  • Updated Figure: Intel Stratix 10 GX FPGA Board - Clock Inputs and Default Frequencies in On-Board Oscillators
2019.06.11

Updated Table SW1 DIP Switch Default Settings (Board TOP) in the section Default Switch and Jumper Settings to clarify that MSEL [0] is tied to Vcc
2019.03.29
  • Added featured device information in Table: Stratix® 10 GX FPGA Development Kit Versions.
  • Renamed the USB-Blaster to Altera® FPGA Download Cable II.
  • Labeled the components of the board in the following:
    • Figure: Stratix® 10 GX FPGA Development Board Image - Front
    • Figure: Stratix® 10 GX FPGA Development Board Image - Rear
2018.11.27

Updated figure in Default Switch and Jumper Settings. Default position representation of M5JTAG_BYPASSn signal in switch SW6 is corrected to OFF position to ensure it matches the table description
2018.07.20

Added FPGA device variant GX to the document title
2017.12.28

Corrected errors in pin table in HiLo External Memory Interface
2017.12.22

Updated tables in HiLo External Memory Interface, QSFP and DisplayPort
2017.10.11
2017.04.17

Engineering Silicon (ES) Release
2016.12.23

Preliminary Release
Level Two Title