Intel® Stratix® 10 GX FPGA Development Kit User Guide

ID 683674
Date 4/02/2020
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4.6.8. SDI Video Input/Output Ports

The Intel® Stratix® 10 GX FPGA development board includes a SDI port, which consists of a M23428G-33 cable driver and a M23544G-14 cable equalizer. The PHY devices from Macom interface to single-ended HDBNC connectors.

The cable driver supports operation from 125 Mbps to 11.88 Gbps. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Table 27.  SDI Video Output Standards for the SD and HD Input
SD_HD Input Supported Output Standards Rise Time
0 SMPTE 424M, SMPTE 292M Faster
1 SMPTE 259M Slower
Table 28.  SDI Video Output Interface Pin Assignments, Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
U20.9 SDI_SD_HDn AY40 1.8V
U20.5 SDI_TX_RESET
U20.1 SDI_TXCAP_N G46 1.4V PCML
U20.16 SDI_TXCAP_P G47 1.4V PCML
U20.10 SDI_TXDRV_N
U20.11 SDI_TXDRV_P

The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD and 3.0, 6.0, and 11.88 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Table 29.  SDI Cable Equalizer Lengths
Cable Type Data Rate (Mbps) Maximum Cable Length (m)
Belden 1694A 270 400
Belden 1694A 1485 140
Belden 1694A 2970 120
Table 30.  SDI Video Input Interface Pin Assignments, Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
U21.10 MF0_BYPASS BA40 1.8V
U21.19 MF1_AUTO_SLEEP BA39 1.8V
U21.21 MF2_MUTE BB39 1.8V
U21.22 MF3_XSD
U21.6 MODE_SEL
U21.11 MUTEREF
U21.4 SDI_EQIN_N1
U21.3 SDI_EQIN_P1
U21.14 SDO_N/SDI_RX_N G42 1.4V PCML
U21.15 SDO_P/SDI_RX_P G43 1.4V PCML