Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card High Pin Count (HPC) Low Pin Count (LPC)
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.9.1.5. FMC Loopback Card

The Intel® Stratix® 10 GX FPGA development kit provides one FMC mezzanine interface port connected to the Intel® Stratix® 10 GX FPGA for interfacing to the Intel FMC add-in boards as shown in the figure below.

The FMC interface is mechanically compliant with the Vita57.1 specification for attaching a single width mezzanine module. However, in terms of signal connections, the Intel

FMC interface is not fully compliant with the Vita 57.1 specification. Instead, it contains a subset of the Vita57.1 interface signal to the connector as shown in the FMCA signal assignment tables.
Figure 16.  Intel® Stratix® 10 GX FPGA Development Kit FMC Block Diagram

The following table shows the complete signal connections assigned for Intel FMC interface at the FMCA port.

Table 38.  FMCA Connector (J13) Signal Assignments
Row Number K J H G F E D C B A
1 NC GND VREF_FMCA GND FMCA_M2C_PG GND FMCA_C2M_PG GND NC GND
2 GND NC FMCA_PRSNTn FMCA_CLK_M2C_P1 GND NC GND FMCA_DP_C2M_P0 GND FMCA_DP_M2C_P1
3 GND NC GND FMCA_CLK_M2C_N1 GND NC GND FMCA_DP_C2M_N0 GND FMCA_DP_M2C_N1
4 FMCA_DP_M2C_P10 GND FMCA_CLK_M2C_P0 GND NC GND FMCA_GBTCLK_M2C_P0 GND FMCA_DP_M2C_P9 GND
5 FMCA_DP_M2C_N10 GND FMCA_CLK_M2C_N0 GND NC GND FMCA_GBTCLK_M2C_N0 GND FMCA_DP_M2C_N9 GND
6 GND NC GND FMCA_LA_RX_CLK_P0 GND NC GND FMCA_DP_M2C_P0 GND FMCA_DP_M2C_P2
7 FMCA_DP_M2C_P11 GND FMCA_LA_TX_P0 FMCA_LA_RX_CLK_N0 NC NC GND FMCA_DP_M2C_N0 GND FMCA_DP_M2C_N2
8 FMCA_DP_M2C_N11 GND FMCA_LA_TX_N0 GND NC GND FMCA_LA_RX_CLK_P1 GND FMCA_DP_M2C_P8 GND
9 GND NC GND FMCA_LA_RX_P0 GND NC FMCA_LA_RX_CLK_N1 GND FMCA_DP_M2C_N8 GND
10 FMCA_DP_M2C_P12 GND FMCA_LA_TX_P1 FMCA_LA_RX_N0 NC NC GND FMCA_LA_RX_P1 GND FMCA_DP_M2C_P3
11 FMCA_DP_M2C_N12 GND FMCA_LA_TX_N1 GND NC GND FMCA_LA_TX_P2 FMCA_LA_RX_N1 GND FMCA_DP_M2C_N3
12 GND NC GND FMCA_LA_RX_P2 GND NC FMCA_LA_TX_N2 GND FMCA_DP_M2C_P7 GND
13 FMCA_DP_M2C_P13 GND FMCA_LA_TX_P3 FMCA_LA_RX_N2 NC NC GND GND FMCA_DP_M2C_N7 GND
14 FMCA_DP_M2C_N13 GND FMCA_LA_TX_N3 GND NC GND FMCA_LA_TX_P4 FMCA_LA_RX_P3 GND FMCA_DP_M2C_P4
15 GND NC GND FMCA_LA_RX_P4 GND NC FMCA_LA_TX_N4 FMCA_LA_RX_P3 GND FMCA_DP_M2C_P4
16 FMCA_DP_M2C_P14 GND FMCA_LA_TX_P5 FMCA_LA_RX_N4 NC NC GND GND FMCA_DP_M2C_P6 GND
17 FMCA_DP_M2C_N14 GND FMCA_LA_TX_N5 GND NC GND FMCA_LA_TX_P6 GND FMCA_DP_M2C_N6 GND
18 GND NC GND FMCA_LA_RX_P6 GND NC FMCA_LA_TX_N6 FMCA_LA_RX_P5 GND FMCA_DP_M2C_P5
19 FMCA_DP_M2C_P15 GND FMCA_LA_TX_P7 FMCA_LA_RX_N6 NC NC GND FMCA_LA_RX_N5 GND FMCA_DP_M2C_N5
20 FMCA_DP_M2C_N15 GND FMCA_LA_TX_N7 GND NC GND FMCA_LA_TX_P8 GND FMCA_GBTCLK_M2C_N1 GND
21 GND NC GND FMCA_LA_RX_P8 GND NC FMCA_LA_TX_N8 GND FMCA_GBTCLK_M2C_N1 GND
22 FMCA_DP_C2M_P10 GND FMCA_LA_TX_P9 FMCA_LA_RX_N8 NC NC GND FMCA_LA_RX_P7 GND FMCA_DP_C2M_P1
23 FMCA_DP_C2M_N10 GND FMCA_LA_TX_N9 GND NC GND FMCA_LA_TX_P11 FMCA_LA_RX_N7 GND FMCA_DP_C2M_N1
24 GND NC GND FMCA_LA_RX_P9 GND NC FMCA_LA_TX_N11 GND FMCA_DP_C2M_P9 GND
25 FMCA_DP_C2M_P11 GND FMCA_LA_TX_P10 FMCA_LA_RX_N9 NC NC GND GND FMCA_DP_C2M_N9 GND
26 FMCA_DP_C2M_N11 GND FMCA_LA_TX_N10 GND NC GND FMCA_LA_TX_P13 FMCA_LA_RX_P11 GND FMCA_DP_C2M_P2
27 GND NC GND FMCA_LA_RX_P10 GND NC FMCA_LA_TX_N13 FMCA_LA_RX_N11 GND FMCA_DP_C2M_N2
28 FMCA_DP_C2M_P12 GND FMCA_LA_TX_P12 FMCA_LA_RX_N10 NC NC GND GND FMCA_DP_C2M_P8 GND
29 FMCA_DP_C2M_N12 GND FMCA_LA_TX_N12 GND NC GND FMCA_JTAG_TCK GND FMCA_DP_C2M_N8 GND
30 GND NC GND FMCA_LA_RX_P12 GND NC FMCA_JTAG_TDI FMCA_3P3V_SCL GND FMCA_DP_C2M_P3
31 FMCA_DP_C2M_P13 GND FMCA_LA_TX_P14 FMCA_LA_RX_N12 NC NC FMCA_JTAG_TDO FMCA_3P3V_SDA GND FMCA_DP_C2M_N3
32 FMCA_DP_C2M_N13 GND FMCA_LA_RX_N14 GND NC GND 3.3V GND FMCA_DP_C2M_P7 GND
33 GND NC GND FMCA_LA_RX_P13 GND NC FMCA_JTAG_TMS GND FMCA_DP_C2M_N7 GND
34 FMCA_DP_C2M_P14 GND FMCA_LA_TX_P15 FMCA_LA_RX_N13 NC NC FMCA_JTAG_RST FMCA_GA0 GND FMCA_DP_C2M_P4
35 FMCA_DP_C2M_N14 GND FMCA_LA_TX_N15 GND NC GND FMCA_GA1 12V GND FMCA_DP_C2M_N4
36 GND NC GND FMCA_LA_RX_P14 GND NC 3.3V GND FMCA_DP_C2M_N6 GND
37 FMCA_DP_C2M_P15 GND FMCA_LA_TX_P16 FMCA_LA_RX_N14 NC NC GND 12V FMCA_DP_C2M_N6 GND
38 FMCA_DP_C2M_N15 GND FMCA_LA_TX_N16 GND NC GND 3.3V GND GND FMCA_DP_C2M_P5
39 GND NC GND A10_VCCIO_FMCA GND A10_VCCIO_FMCA GND 3.3V GND FMCA_DP_C2M_N5
40 NC GND A10_VCCIO_FMCA GND A10_VCCIO_FMCA GND 3.3V GND NC GND
41 NC GND A10_VCCIO_FMCA GND A10_VCCIO_FMCA GND 3.3V GND NC GND
      LPC Connector LPC Connector     HPC Connector HPC Connector    

High Pin Count (HPC)

The High Pin Count FMC connections are assigned to columns G and H in the FMCA connector as shown. The HPC signaling follows the Vita57.1 standard.

Low Pin Count (LPC)

The Low Pin Count FMC connections are assigned to columns C and D in the FMCA connector as shown. The LPC signaling follows the Vita57.1 standard.

Level Two Title