Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.2. MAX V CPLD System Controller

The development board utilizes the EPM2210 System Controller, an Intel MAX® V CPLD for the following purposes:
  • FPGA configuration from flash memory
  • Power consumption monitoring
  • Temperature monitoring
  • Fan control
  • Control registers for clocks
  • Control registers for remote update system
Table 11.  MAX V CPLD System Controller Device Pin-Out
Schematic Signal Name Pin Number I/O Standard Description
FMCA_PRSTn G1 1.8V FMC present
FPGA_AVST_CLK J2 1.8V Avalon stream clock
USB_MAX5_CLK H5 1.8V 48 MHz USB clock
CLK_CONFIG J5 1.8V 125 MHz configuration clock
FPGA_nSTATUS J4 1.8V Configuration nSTATUS signal
FPGA_CONF_DONE K1 1.8V Configuration DONE signal
USB_CFG2 K2 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG3 K5 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG4 L1 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG5 L2 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG6 K3 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG12 M1 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG7 M2 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG8 L4 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG9 L3 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG10 N1 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG0 M4 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG11 N2 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG1 M3 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG13 N3 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

USB_CFG14 P2 1.8V

MAX® V to Intel® MAX® 10 Intel® FPGA Download Cable bus

FPGA_INIT_DONE G4 1.8V Initialization done signal
FPGA_AVST_VALID F5 1.8V Avalon stream valid signal
FPGA_AVST_READY H1 1.8V Avalon stream ready signal
FMCA_C2M_PWRGD R16 1.8V FMC card to mezzanine power good signal
M5_JTAG_TCK P3 1.8V

Dedicated MAX® V JTAG clock

M5_JTAG_TDI L6 1.8V

Dedicated MAX® V JTAG data in

M5_JTAG_TDO M5 1.8V

Dedicated MAX® V JTAG data out

M5_JTAG_TMS N4 1.8V

Dedicated MAX® V JTAG mode select

MAX_RESETn C5 2.5V

MAX® V reset signal

Si516_FS A4 2.5V Si516 device frequency select signal
OVERTEMP E1 2.5V FAN PWM control signal
CLK0_FINC E9 2.5V Si5341A device frequency increment signal
CLK0_FDEC A10 2.5V Si5341A device frequency decrement signal
MAX_CONF_DONE D7 2.5V Configuration done LED signal
CLK0_OEn B12 2.5V Si5341A device enable signal
CLK1_RSTn C11 2.5V Si5341A device reset signal
PGM_SEL A7 2.5V Program Select push button signal
PGM_CONFIG A6 2.5V Program Configuration push button signal
PGM_LED0 D6 2.5V Program LED0 signal
PGM_LED1 C6 2.5V Program LED1 signal
PGM_LED2 B7 2.5V Program LED2 signal
FACTORY_LOAD B5 2.5V Load factory image DIP switch signal
MAX_ERROR C7 2.5V Configuration error LED
MAX_LOAD B6 2.5V Configuration loading LED
FPGA_PR_REQUEST T4 1.8V Partial reconfiguration request signal
FLASH_ADDR1 F15 1.8V

Flash address bus
FLASH_ADDR2 G16 1.8V

Flash address bus
FLASH_ADDR3 G15 1.8V

Flash address bus
FLASH_ADDR4 H16 1.8V

Flash address bus
FLASH_ADDR5 H15 1.8V

Flash address bus
FLASH_ADDR6 F16 1.8V

Flash address bus
FLASH_ADDR7 G14 1.8V

Flash address bus
FLASH_ADDR8 D16 1.8V

Flash address bus
FLASH_ADDR9 E15 1.8V

Flash address bus
FLASH_ADDR10 E16 1.8V

Flash address bus
FLASH_ADDR11 H14 1.8V

Flash address bus
FLASH_ADDR12 D15 1.8V

Flash address bus
FLASH_ADDR13 F14 1.8V

Flash address bus
FLASH_ADDR14 C14 1.8V

Flash address bus
FLASH_ADDR15 C15 1.8V

Flash address bus
FLASH_ADDR16 H3 1.8V

Flash address bus
FLASH_ADDR17 H2 1.8V

Flash address bus
FLASH_ADDR18 E13 1.8V

Flash address bus
FLASH_ADDR19 F13 1.8V

Flash address bus
FLASH_ADDR20 G13 1.8V

Flash address bus
FLASH_ADDR21 G12 1.8V

Flash address bus
FLASH_ADDR22 E12 1.8V

Flash address bus
FLASH_ADDR23 H13 1.8V Flash address bus
FLASH_ADDR24 G5 1.8V Flash address bus
FLASH_ADDR25 J13 1.8V Flash address bus
FPGA_PR_DONE J16 1.8V Partial reconfiguration done signal
CLK_MAXV_50M J12 1.8V 50 MHz MAX® V clock
MAXV_OSC_CLK1 H12 1.8V 125 MHz MAX® V clock
FLASH_DATA0 J15 1.8V

Flash data bus
FLASH_DATA1 L16 1.8V

Flash data bus
FLASH_DATA2 L14 1.8V

Flash data bus
FLASH_DATA3 K14 1.8V

Flash data bus
FLASH_DATA4 L13 1.8V

Flash data bus
FLASH_DATA5 L15 1.8V

Flash data bus
FLASH_DATA6 M15 1.8V

Flash data bus
FLASH_DATA7 M16 1.8V

Flash data bus
FLASH_DATA8 K16 1.8V

Flash data bus
FLASH_DATA9 K15 1.8V

Flash data bus
FLASH_DATA10 J14 1.8V

Flash data bus
FLASH_DATA11 K13 1.8V

Flash data bus
FLASH_DATA12 L12 1.8V

Flash data bus
FLASH_DATA13 N16 1.8V

Flash data bus
FLASH_DATA14 M13 1.8V

Flash data bus
FLASH_DATA15 L11 1.8V

Flash data bus
FLASH_CEn0 D14 1.8V

Flash chip enable 0
FLASH_OEn P14 1.8V

Flash output enable
FLASH_RDYBSYn0 F12 1.8V

Flash ready/busy 0
FLASH_RESETn D13 1.8V

Flash reset
FLASH_CLK N15 1.8V

Flash clock
FLASH_ADVn N14 1.8V

Flash address valid
FLASH_CEn1 F11 1.8V

Flash chip enable 1
FPGA_PR_ERROR K12 1.8V Partial reconfiguration error signal
FPGA_CvP_CONFDONE M14 1.8V CvP configuration done signal
FLASH_RDYBSYn1 P12 1.8V Flash ready/busy 1
FPGA_CONFIG_D0 R1 1.8V

FPGA configuration data bus
FPGA_CONFIG_D1 T2 1.8V

FPGA configuration data bus
FPGA_CONFIG_D2 N6 1.8V

FPGA configuration data bus
FPGA_CONFIG_D3 N5 1.8V

FPGA configuration data bus
FPGA_CONFIG_D4 N7 1.8V

FPGA configuration data bus
FPGA_CONFIG_D5 N8 1.8V

FPGA configuration data bus
FPGA_CONFIG_D6 M12 1.8V

FPGA configuration data bus
FPGA_CONFIG_D7 T13 1.8V

FPGA configuration data bus
FPGA_CONFIG_D8 T15 1.8V

FPGA configuration data bus
FPGA_CONFIG_D9 R13 1.8V

FPGA configuration data bus
FPGA_CONFIG_D10 P4 1.8V

FPGA configuration data bus
FPGA_CONFIG_D11 R3 1.8V

FPGA configuration data bus
FPGA_CONFIG_D12 T10 1.8V

FPGA configuration data bus
FPGA_CONFIG_D13 P5 1.8V

FPGA configuration data bus
FPGA_CONFIG_D14 R4 1.8V

FPGA configuration data bus
FPGA_CONFIG_D15 R5 1.8V

FPGA configuration data bus
MAX5_OEn N10 1.8V

MAX® V output enable

MAX5_CSn T11 1.8V

MAX® V chip select

MAX5_WEn R11 1.8V

MAX® V write enable

MAX5_CLK N11 1.8V

MAX® V clock

MAX5_BEn0 R10 1.8V

MAX® V byte enable

MAX5_BEn1 M10 1.8V

MAX® V byte enable

MAX5_BEn2 T12 1.8V

MAX® V byte enable

MAX5_BEn3 P10 1.8V

MAX® V byte enable

CPU_RESETn K4 1.8V CPU reset button
I2C_1.8V_SCL P13 1.8V 1.8V I2C bus
I2C_1.8V_SDA R14 1.8V 1.8V I2C bus
OVERTEMPn_1.8V N13 1.8V Over temperature signal
TSENSE_ALERTn_1.8V T7 1.8V Temperature sense alert signal
QSPI_SS0_MSEL0 R12 1.8V QSPI slave select 0/ MSEL [0] configuration select
MSEL1 P11 1.8V MSEL [1] configuration select
MSEL2 M11 1.8V MSEL [2] configuration select
SDI_MF2_MUTE R7 1.8V SDI device MF2
SDI_MF0_BYPASS P8 1.8V SDI device MF0
SDI_MF1_AUTO_SLEEP R6 1.8V SDI device MF1
SDI_TX_SD_HDn P6 1.8V SDI device SD/HD
FPGA_nCONFIG E14 1.8V nCONFIG configuration signal
Level Two Title