Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.3. HiLo External Memory Interface

This section describes the Intel® Stratix® 10 GX FPGA development board's external memory interface support and also their signal names, types and connectivity relative to the Intel® Stratix® 10 GX FPGA.
The HiLo connector supports plugins for the following memory interfaces:
  • DDR3 x72 (included in the kit)
  • DDR4 x72 (included in the kit)
  • RLDRAM3 x36 (included in the kit)
Table 18.  HiLo EMI Pin Assignments
Board Reference - HiLo Pin Number HiLo Schematic Signal Name FPGA Pin Number I/O Standard
F1 MEM_ADDR_CMD0 K38 Adjustable
H1 MEM_ADDR_CMD1 L37 Adjustable
F2 MEM_ADDR_CMD2 M37 Adjustable
G2 MEM_ADDR_CMD3 M38 Adjustable
H2 MEM_ADDR_CMD4 J39 Adjustable
J2 MEM_ADDR_CMD5 J38 Adjustable
K2 MEM_ADDR_CMD6 K39 Adjustable
G3 MEM_ADDR_CMD7 L39 Adjustable
J3 MEM_ADDR_CMD8 P37 Adjustable
L3 MEM_ADDR_CMD9 R37 Adjustable
E4 MEM_ADDR_CMD10 N37 Adjustable
F4 MEM_ADDR_CMD11 P38 Adjustable
G4 MEM_ADDR_CMD12 P35 Adjustable
H4 MEM_ADDR_CMD13 K36 Adjustable
J4 MEM_ADDR_CMD14 K37 Adjustable
K4 MEM_ADDR_CMD15 N36 Adjustable
M1 MEM_ADDR_CMD16 L36 Adjustable
M2 MEM_ADDR_CMD17 T35 Adjustable
N2 MEM_ADDR_CMD18 R36 Adjustable
L4 MEM_ADDR_CMD19 L35 Adjustable
P5 MEM_ADDR_CMD20 L40 Adjustable
M5 MEM_ADDR_CMD21 K40 Adjustable
P1 MEM_ADDR_CMD22 G38 Adjustable
R4 MEM_ADDR_CMD23 H38 Adjustable
M4 MEM_ADDR_CMD24 G40 Adjustable
R3 MEM_ADDR_CMD25 F40 Adjustable
L2 MEM_ADDR_CMD26 P36 Adjustable
K1 MEM_ADDR_CMD27 E40 Adjustable
P2 MEM_ADDR_CMD28 D40 Adjustable
N4 MEM_ADDR_CMD29 R33 Adjustable
P4 MEM_ADDR_CMD30 J40 Adjustable
N3 MEM_ADDR_CMD31 H40 Adjustable
V2 MEM_CLK_N G39 Adjustable
V1 MEM_CLK_P F39 Adjustable
B10 MEM_DMA0 E27 Adjustable
C4 MEM_DMA1 M27 Adjustable
B17 MEM_DMA2 V30 Adjustable
F17 MEM_DMA3 P25 Adjustable
M16 MEM_DMB0 K32 Adjustable
U16 MEM_DMB1 J33 Adjustable
U11 MEM_DMB2 F37 Adjustable
U6 MEM_DMB3 C36 Adjustable
R6 MEM_DQ_ADDR_CMD0 T31 Adjustable
T1 MEM_DQ_ADDR_CMD1 R34 Adjustable
R2 MEM_DQ_ADDR_CMD2 R31 Adjustable
T2 MEM_DQ_ADDR_CMD3 U33 Adjustable
U2 MEM_DQ_ADDR_CMD4 U34 Adjustable
U3 MEM_DQ_ADDR_CMD5 T34 Adjustable
T4 MEM_DQ_ADDR_CMD6 U32 Adjustable
U4 MEM_DQ_ADDR_CMD7 V32 Adjustable
T5 MEM_DQ_ADDR_CMD8 P33 Adjustable
A4 MEM_DQA0 B27 Adjustable
B4 MEM_DQA1 F27 Adjustable
B5 MEM_DQA2 G27 Adjustable
B6 MEM_DQA3 C27 Adjustable
A8 MEM_DQA4 C26 Adjustable
B8 MEM_DQA5 B25 Adjustable
B9 MEM_DQA6 D26 Adjustable
A10 MEM_DQA7 D25 Adjustable
B1 MEM_DQA8 H27 Adjustable
B2 MEM_DQA9 H26 Adjustable
C2 MEM_DQA10 J25 Adjustable
C3 MEM_DQA11 H25 Adjustable
E3 MEM_DQA12 L27 Adjustable
D4 MEM_DQA13 L26 Adjustable
D1 MEM_DQA14 G25 Adjustable
D2 MEM_DQA15 K27 Adjustable
A12 MEM_DQA16 U29 Adjustable
B12 MEM_DQA17 T30 Adjustable
B13 MEM_DQA18 T29 Adjustable
B14 MEM_DQA19 V26 Adjustable
C15 MEM_DQA20 U30 Adjustable
A16 MEM_DQA21 V25 Adjustable
B16 MEM_DQA22 U28 Adjustable
A18 MEM_DQA23 U27 Adjustable
C16 MEM_DQA24 T25 Adjustable
D16 MEM_DQA25 N27 Adjustable
E16 MEM_DQA26 L25 Adjustable
F16 MEM_DQA27 U25 Adjustable
D17 MEM_DQA28 N26 Adjustable
C18 MEM_DQA29 R26 Adjustable
D18 MEM_DQA30 P26 Adjustable
E18 MEM_DQA31 N25 Adjustable
E2 MEM_DQA32 F25 Adjustable
G16 MEM_DQA33 M25 Adjustable
H16 MEM_DQB0 K34 Adjustable
J16 MEM_DQB1 K33 Adjustable
K16 MEM_DQB2 N33 Adjustable
L16 MEM_DQB3 M33 Adjustable
H17 MEM_DQB4 J34 Adjustable
K17 MEM_DQB5 N32 Adjustable
K18 MEM_DQB6 N31 Adjustable
L18 MEM_DQB7 M34 Adjustable
M17 MEM_DQB8 E34 Adjustable
N18 MEM_DQB9 F34 Adjustable
P17 MEM_DQB10 H35 Adjustable
P18 MEM_DQB11 J35 Adjustable
R18 MEM_DQB12 G35 Adjustable
T16 MEM_DQB13 H36 Adjustable
T17 MEM_DQB14 F35 Adjustable
T18 MEM_DQB15 H33 Adjustable
U15 MEM_DQB16 D34 Adjustable
T14 MEM_DQB17 E38 Adjustable
U14 MEM_DQB18 D38 Adjustable
V14 MEM_DQB19 E37 Adjustable
T13 MEM_DQB20 D35 Adjustable
T12 MEM_DQB21 D39 Adjustable
U12 MEM_DQB22 E39 Adjustable
V12 MEM_DQB23 H37 Adjustable
T10 MEM_DQB24 A37 Adjustable
U10 MEM_DQB25 B38 Adjustable
V10 MEM_DQB26 C38 Adjustable
T9 MEM_DQB27 A38 Adjustable
T8 MEM_DQB28 C37 Adjustable
U8 MEM_DQB29 B37 Adjustable
U7 MEM_DQB30 B35 Adjustable
V6 MEM_DQB31 C35 Adjustable
R16 MEM_DQB32 J36 Adjustable
T6 MEM_DQB33 D36 Adjustable
V5 MEM_DQS_ADDR_CMD_N T32 Adjustable
V4 MEM_DQS_ADDR_CMD_P R32 Adjustable
A7 MEM_DQSA_N0 F26 Adjustable
A3 MEM_DQSA_N1 K26 Adjustable
A15 MEM_DQSA_N2 V27 Adjustable
G18 MEM_DQSA_N3 R27 Adjustable
A6 MEM_DQSA_P0 E26 Adjustable
A2 MEM_DQSA_P1 J26 Adjustable
A14 MEM_DQSA_P2 V28 Adjustable
F18 MEM_DQSA_P3 T26 Adjustable
J18 MEM_DQSB_N0 L31 Adjustable
V18 MEM_DQSB_N1 G34 Adjustable
V17 MEM_DQSB_N2 F36 Adjustable
V9 MEM_DQSB_N3 A35 Adjustable
H18 MEM_DQSB_P0 L32 Adjustable
U18 MEM_DQSB_P1 G33 Adjustable
V16 MEM_DQSB_P2 E36 Adjustable
V8 MEM_DQSB_P3 A36 Adjustable
A11 MEM_QKA_P0 C25 Adjustable
B18 MEM_QKA_P1 T27 Adjustable
M18 MEM_QKB_P0 L34 Adjustable
V13 MEM_QKB_P1 G37 Adjustable
Level Two Title