Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.7.1. On-Board Oscillators

Figure 11.  Intel® Stratix® 10 GX FPGA Board - Clock Inputs and Default Frequencies
Table 31.  On-Board Oscillators
Source Schematic Signal Name Frequency I/O Standard Intel® Stratix® 10 FPGA Pin Number Application
U7 REFCLK1_P 155.52 MHz LVDS AM41 Transceiver reference clocks Bank 1D
REFCLK1_N LVDS AM40
REFCLK_QSFP1_P 644.53125 MHz LVDS Y38 QSFP reference clocks
REFCLK_QSFP1_N LVDS Y37
REFCLK_DP_P 135 MHz LVDS AK38 DisplayPort reference clocks
REFCLK_DP_N LVDS AK37
REFCLK4_P 156.25 MHz LVDS AF9 Transceiver reference clocks Bank 4E
REFCLK4_N LVDS AF10
REFCLK_FMCA_P 625 MHz LVDS AT9 FMC reference clocks
REFCLK_FMCA_N LVDS AT10
CLK_ENET_P 125 MHz LVDS AN27 Ethernet clock
CLK_ENET_N LVDS AN28
FPGA_OSC_CLK1 125 MHz LVDS BA22 FPGA configuration clock
MAXV_OSC_CLK1 125 MHz LVDS – MAX® V clock
CLK_CONFIG 125 MHz LVDS – MAX® V clock
U9 CLK_FPGA_50M 50 MHz 1.8V LVCMOS BH33 FPGA clock
CLK_MAXV_50M 50 MHz 1.8V LVCMOS – MAX V clock
CLK_HILO_P 133 MHz LVDS M35 HiLo memory clock
CLK_HILO_N LVDS N35
CLK_FOGA_B3L_P 100 MHz LVDS J20 FPGA clock for Bank 3L
CLK_FPGA_B3L_N LVDS J19
PCIE_OB_REFCLK_P 100 MHz LVDS AP41 On board PCIe* reference clock
PCIE_ON_REFCLK_N LVDS AP40
X1 REFCLK_SDI_P 148.5 MHz LVDS P41 SDI reference clocks
REFCLK_SDI_N LVDS P40
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