Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

6.5. Using Logic Lock Regions in Combination with Design Partitions

You can optimize timing in a design by placing entities that share significant logical connectivity close to each other on the device.

By default, the Fitter attempts to place closely connected entities in the same area of the device. However, without constraint, this same placement is not assured for each compilation. You can use Logic Lock regions, together with design partitions, to ensure that logically connected entities retain optimal placement from one compilation to the next.

Using Logic Lock regions in combination with design partitions allows you to preserve the location and performance of a block, so that the Fitter focuses time and effort on other portions of the design.

Note: For more details about these techniques, refer to Quartus Prime Pro Edition User Guide: Block-Based Design
To use the Design Partition Planner in conjunction with the Chip Planner to readily create partitions and define Logic Lock regions, follow these steps:
  1. On the Compilation Dashboard, double-click Plan to compile through that Fitter stage, or run a full compilation.
  2. Open the Chip Planner and the Design Partition Planner:
    • Click Tools > Chip Planner
    • Click Tools > Design Partition Planner
  3. In the Chip Planner, double-click Report Design Partitions in the Tasks pane. The Chip Planner displays the physical locations of design partitions using the same colors as the entities in the Design Partition Planner.
    Figure 128. Design Partition Planner Overlaying Chip Planner

  4. In the Chip Planner, click View > Bird's Eye View
  5. In the Design Partition Planner, drag all the larger entities out from their parents. Alternatively, you can right-click the entity and click Extract from Parent.
    The Chip Planner displays the physical placement of the entities shown in the Design Partition Planner, with consistent colors between the two tools. You can view physical placement in the Chip Planner and connectivity in the Design Partition Planner.
  6. Identify entities that are unsuitable to place in Logic Lock regions:
    • The Chip Planner shows an entity to be physically dispersed over noncontiguous areas of the device.
    • The Design Partition Planner shows an entity to have a large number of connections to other entities.
  7. Drag the entities that are unsuitable for placement in Logic Lock regions back to the parent entities. Alternatively, right-click the entity and click Collapse to Parent.
  8. Create a partition for each remaining entity by right-clicking the entity, and then clicking Create Design Partition.
  9. Create a Logic Lock region for each partition by right-clicking the partition, and then clicking Create Logic Lock Region.