Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

6.2. Design Floorplan Analysis in Chip Planner

The Chip Planner simplifies floorplanning by allowing you to view and constrain design logic within a visual display of the FPGA chip resources. You can use the Chip Planner to view and modify the logic placement, connections, and routing paths after running the Fitter. You can also make assignment changes, such as creating and deleting Logic Lock, clock region, and resource assignments.
Figure 75. The Chip Planner