Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Public

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Document Table of Contents

4.4. Area Optimization Revision History

The following revision history applies to this chapter:

Document Version Quartus® Prime Version Changes
2024.04.01 24.1
  • Applied initial Altera rebranding throughout.
2023.10.02 23.3
  • Updated Guideline: Use Register Packing to include link to help topic with list of reasons that prevent register packing.
2023.07.24 23.2
  • Added new Route Stage Reports section to describe latest routing reports to alleviate routing congestion.
2023.04.03 23.1
  • Revised Guideline: Use Register Packing to describe latest changes for DSP Register Packing and DSP_REGISTER_PACKING_LEVEL entity assignments and reporting.
2022.01.07 21.4
  • Corrected syntax error in Scripting Support topic.
  • Added link to Fitter Reports topic.
  • Added new Design Assistant Recommendations topic.
  • Revised Compilation Messages topic.
  • Added Chip Planner Visualization topic.
  • Added reference to Design Assistant to Guideline: Optimize Source Code topic.
  • Revised Guideline: Optimize Synthesis for Area, Not Speed topic to mention Aggressive Area Optimization Mode.
  • Revised Guideline: Optimize Synthesis for Area, Not Speed topic to mention Aggressive Area Optimization Mode and remove Speed Optimization Technique for Clock Domains reference.
  • Revised Guideline: Retarget Memory Blocks topic to mention use of appropriate embedded memory IP.
  • Revised Guideline: Retarget or Balance DSP Blocks topic to mention use of fractal synthesis.
  • Added Guideline: Report Pipelining Information topic.
  • Added reference to Global Router Wire Utilization Map report to Guideline: Optimize Source Code topic.
  • Removed references to obsolete Timing Optimization Advisor.
2018.10.18 18.1
  • Corrected broken link to Optimization Modes Help topic.
2018.09.24 18.1
  • Divided topic: Resource Utilization into topics: Resource Utilization Information, Flow Summary Report, Fitter Reports, Analysis and Synthesis Reports, and Compilation Messages.
2018.07.03 18.0 Fixed typo and added links in topic Guideline: Retarget Memory Blocks.
2017.05.08 17.0
  • Removed information about deprecated Integrated Synthesis
  • Revised topics: Resolving Resource Utilization Issues, Guideline: Optimize Synthesis for Area, Not Speed
2016.10.31 16.1
  • Implemented Intel rebranding.
2016.05.02 16.0
  • Removed information about deprecated physical synthesis options.
2015.11.02 15.1 Changed instances of Quartus II to Intel Quartus Prime.
2014.12.15 14.1 Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical Synthesis Optimizations to Compiler Settings.
June 2014 14.0
  • Removed Cyclone III and Stratix III devices references.
  • Removed Macrocell-Based CPLDs related information.
  • Updated template.
May 2013 13.0 Initial release.