Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

7.4.5. adjust_pll_refclk


Changes the IOPLL frequencies by modifying the input reference clock frequency. The following stipulations apply:
  • Maintain the original refclk and outclk ratios.
  • The IOPLLs you change cannot generate IP clocks.
  • Cascaded IOPLLs must connect directly (no clock gates in between them).
  • IOPLLs cannot be in 'nondedicated' compensation modes.
  • For all IOPLLs, outclks duty cycle equals 50 and phase shift equals 0.
  • No support for Agilex® 7 devices.


The following example adjusts the *pll_main* IOPLL by modifying the input clock frequency to 100 MHz.

adjust_pll_refclk -to {*pll_main*} -refclk 100


Instance name of upstream IOPLL that you want to adjust. Escape any [ or ] characters in the target name.
New refclk frequency value in MHz.