Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

2.3. RTL Viewer Overview

The RTL Viewer allows you to view a register transfer level (RTL) graphical representation of Quartus® Prime Pro Edition synthesis results or third-party netlist files in the Quartus® Prime software.

You can view results after Analysis and Elaboration for designs that use any supported Quartus® Prime design entry method, including Verilog HDL Design Files (.v), SystemVerilog Design Files (.sv), VHDL Design Files (.vhd), AHDL Text Design Files (.tdf), or schematic Block Design Files (.bdf).

You can also view the hierarchy of atom primitives (such as device logic cells and I/O ports) for designs that generate Verilog Quartus Mapping File (.vqm) or Electronic Design Interchange Format (.edf) files through a synthesis tool.

The RTL Viewer displays a schematic view of the design netlist after Analysis and Elaboration or after the Quartus® Prime software performs netlist extraction, but before technology mapping and synthesis or fitter optimizations. This view a preliminary pre-optimization design structure and closely represents the original source design.
  • For designs synthesized with the Quartus® Prime Pro Edition synthesis, this view shows how the Quartus® Prime software interprets the design files.
  • For designs synthesized with a third-party synthesis tool, this view shows the netlist that the synthesis tool generates.

To run the RTL Viewer for an Quartus® Prime project, first analyze the design to generate an RTL netlist. To analyze the design and generate an RTL netlist, click Processing > Start > Start Analysis & Elaboration. You can also perform a full compilation on any process that includes the initial Analysis and Elaboration stage of the Quartus® Prime compilation flow.

To open the RTL Viewer, click Tools > Netlist Viewers > RTL Viewer.