Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

5.5.2. Implement Fast Forward Timing Closure Recommendations

In traditional FPGA timing closure flows, the starting point for most design analysis is the critical path. Due to the nature of Hyperflex® architecture and the availability of the Hyper Retimer, it is best to start you timing closure activities from the Retiming Limit Report. Provide the Hyper-Retimer as many optimization opportunities as possible, before having to look into more time intensive and potentially manual timing closure techniques.