Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/01/2024
Document Table of Contents

6. Analyzing and Optimizing the Design Floorplan

Determining the layout (placement) of your design elements into physical resources on the FPGA device is known as floorplanning. Floorplanning is a critical design step that helps to ensure that the Compiler places important design logic in the most effective locations for optimum performance and rapid timing closure.

By default, the Compiler determines the best location for logic placement based on your design characteristics and project settings and constraints. You can use the Quartus® Prime Chip Planner to visualize the available device resources, and then use a variety of constraints to implement specific placement for important logic, and to group blocks together within specific device regions.

For example, you can define a Logic Lock placement constraint to assign design logic to any arbitrary region of physical resources on the target device that you define. When you assign nodes or entities to the Logic Lock region, the Compiler always places that logic inside the region during fitting. You can define the Logic Lock region's size and location.

Figure 73.  Logic Lock Regions in Chip Planner Floorplan

After compilation, you can back-annotate (copy) the Compiler's resource assignments to preserve that same implementation in subsequent compilations. Assignment back-annotation can simplify timing closure by allowing you to lock down placement of your optimized results.