4.3.1. General-Purpose Register File 4.3.2. Arithmetic Logic Unit 4.3.3. Multipy and Divide Units 4.3.4. Floating-Point Unit 4.3.5. Custom Instruction 4.3.6. Reset and Debug Signals 4.3.7. Control and Status Registers 4.3.8. Exception Controller 4.3.9. Interrupt Controller 4.3.10. Memory and I/O Organization 4.3.11. RISC-V based Debug Module 4.3.12. Error Correction Code (ECC)
3. Nios® V/m Processor
The Nios® V/m processor is a microcontroller core developed by Intel based on the RISC-V instruction set and supports the functional units described in this document.
The Nios® V/m processor supports two distinct configurations:
- Applies RV32IAZicsr instruction set.
- Supports five-stages pipeline datapath.
- Applies RV32IZicsr instruction set.
- Supports non-pipeline datapath.