2.3.4. Memory and I/O Organization
You can configure the Nios® V/c processor systems. Consequently, the memory and I/O organization varies from system to system. A Nios® V/c processor core uses one or more of the following ports to provide access to memory and I/O:
- Instruction manager port: An Arm* Advanced Microcontroller Bus Architecture ( AMBA* ) AXI4-Lite Memory-Mapped manager port that connects to instruction memory via system interconnect fabric.
- Data manager port: An AMBA* AXI4-Lite Memory-Mapped manager port that connects to data memory and peripherals via the system interconnect fabric.
Nios® V/c Processor Core Memory Mapped I/O Access: Both data memory and peripherals are mapped into the address space of the data manager port. Nios® V/c processor core uses little-endian byte ordering. Words and half-words are stored in memory with the more-significant bytes at higher addresses. The Nios® V/c processor core does not specify anything about the existence of memory and peripherals. The quantity, type, and connection of memory and peripherals are system dependent.