Nios® V Processor Reference Manual

ID 683632
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.2. Processor Pipeline

The Nios® V/c processor supports a non-pipelined datapath.

Table 4.  Processor Non-pipelined Stages
Stage Denotation Function
F Instruction fetch Pre-decode for register file read
D Instruction decode
  • Decode the instruction
  • Register file read data available
  • Hazard resolution and data forwarding
E Instruction execute
  • ALU operations
  • Memory address calculation
  • Branch resolution
  • CSR read/write
M Memory
  • Memory and multicycle operations
  • Register file write
  • Next PC logic
  • Branch redirection

The Nios® V/c processor implements the general-purpose register file using the M20K memory blocks. The processor takes one clock cycle to read from an M20K location. Therefore, the F-stage initiates register file reads so general-purpose register values are available in D-stage.

One instruction is available in the processor datapath at any time. Instructions flow from F-stage to M-stages without any stalls. Instruction and associated control logic are registered during D-stage, E-stage, and M-stage.

The processor requests the next instruction during the M-stage.

  • For single cycle instructions, the processor makes the request as soon as the single cycle instruction enters M-stage.
  • For multicycle instructions, the processor makes the request as soon as the multicycle instruction completes.