2.2. Processor Pipeline
The Nios® V/c processor supports a non-pipelined datapath.
|Pre-decode for register file read
The Nios® V/c processor implements the general-purpose register file using the M20K memory blocks. The processor takes one clock cycle to read from an M20K location. Therefore, the F-stage initiates register file reads so general-purpose register values are available in D-stage.
One instruction is available in the processor datapath at any time. Instructions flow from F-stage to M-stages without any stalls. Instruction and associated control logic are registered during D-stage, E-stage, and M-stage.
The processor requests the next instruction during the M-stage.
- For single cycle instructions, the processor makes the request as soon as the single cycle instruction enters M-stage.
- For multicycle instructions, the processor makes the request as soon as the multicycle instruction completes.