|A global hardware reset input signal that forces the Nios® V processor to reset immediately.
An optional reset output signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.
- This reset output signal is triggered by the JTAG debugger or niosv-download -r command.
- You can connect this reset output signal to the following input signals:
- To the ndm_reset_in input to reset the core and the timer module.
- To the reset input signal of other components as needed.
An optional reset input signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.
- You can use this signal to trigger reset controller to reset the core and the timer module.
- The reset controller synchronizes the reset (hard reset) and ndm_reset_in signals.
|An optional local reset ports which appear after you enable Add Reset Request Interface parameter. The signal consists of an input resetreq signal and an output ack signal that trigger the Nios® V processor to reset without affecting other components in a Nios® V processor system.
- You can request a reset to the Nios® V processor core by asserting the resetreq signal.
- The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
- Assertion of the resetreq signal in debug mode has no effect on the processor's state.
- The Nios® V processor responds that the reset is successful by asserting the ack signal.
- After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.