4.3.7. Control and Status Registers
Nios® V/g processor's Control and Status Registers (CSR) is both readable and writable. Nios® V/g processor updates the CSR during the E-stage of the pipeline. If a memory or multicycle instruction is pending in M-stage, CSR write does not take place until M-stage completes this instruction. The application's write to CSR is processed by the core after M-stage completes, only if M-stage completes without an exception. If an exception is generated during M-stage, all CSR and other pending instructions are flushed and exception handle takes over.