Nios® V Processor Reference Manual

ID 683632
Date 10/02/2023

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Document Table of Contents

3.1.2. Non-pipelined

Table 20.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Pro Edition Software
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 300 769 0.226 0.173
Intel® Arria® 10 317 770
Intel® Stratix® 10 360 755
Intel Agilex® 7 443 744
Table 21.  Benchmark Parameters for Intel® Quartus® Prime Pro Edition Software
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 23.3.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core (without debug module and internal timer).
  • 128 KB on-chip memory for the instruction and data bus.
  • Interval Timer Core
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 12.1.0
  • CMake Version: 3.26.3
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • fMAX benchmark: superior_performance_optimized_placement_effort
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.