Nios® V Processor Reference Manual

ID 683632
Date 10/02/2023

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Document Table of Contents Accessing Tightly Coupled Memory

TCM occupies standard address space like other memory devices connected via system interconnect fabric. The processor configures the address ranges for TCM (if any).

Access from Processor Core

When TCM is present, the Nios® V/g processor core decodes addresses internally to determine if the requested addresses reside in the TCMs. If the address resides in the TCM, the processor core fetches the instruction from instruction TCM or loads the data from the data TCM. The software accesses TCM using regular load and store instructions. From the software’s perspective, there is no difference in accessing a TCM compared to other memory.

Accessing TCM bypasses cache memory. The processor core functions as if the cache were not present for the address span of the TCM. Instructions for managing the cache do not affect the TCM, even if the instruction specifies an address in TCM.

Access from External AXI4-Lite Manager

Any external AXI4-Lite manager can access any TCMs as RAM in the system if it is connected to the TCM’s AXI4-Lite interface. There can only be a single manager accessing the TCMs at any given time, either the processor core or the external manager. Before any access from external managers, place the processor in standby mode using the WFI instruction.

Intel recommends implementing two interrupts on the Nios® V/g processor core. By controlling the state of the processor, the external manager can ensure that only one manager is accessing the TCMs as follows:
  • First interrupt to initiate the WFI instruction to stall the processor.
  • Second interrupt to resume the processor after the read/write accesses have been completed.