Visible to Intel only — GUID: nik1411172651601
Ixiasoft
Visible to Intel only — GUID: nik1411172651601
Ixiasoft
3.4.1.1. PHY Registers
Addr |
Name |
Bit |
Description |
HW Reset Value |
Access |
---|---|---|---|---|---|
0x300 | PHY_REVID | [31:0] | IP core PHY module revision ID. | 0x02062015 | RO |
0x301 | PHY_SCRATCH | [31:0] | Scratch register available for testing. | 32'b0 | RW |
0x302 | PHY_NAME_0 | [31:0] | First 4 characters of IP core variation identifier string " 40GE pcs " or "100GE pcs ". | RO | |
0x303 | PHY_NAME_1 | [31:0] | Next 4 characters of IP core variation identifier string " 40GE pcs " or "100GE pcs ". | RO | |
0x304 | PHY_NAME_2 | [31:0] | Final 4 characters of IP core variation identifier string " 40GE pcs " or "100GE pcs ". | RO | |
0x310 | PHY_CONFIG | [5] | set_data_lock: Directs the PLL to lock to data. | 6'b0 | RW |
[4] | set_ref_lock: Directs the PLL to lock to the reference clock. | ||||
[3] | rxp_ignore_freq: Directs the IP core to proceed with the internal reset sequence (to reset the RX PLL) without waiting for the RX CDR PLL to lock. | ||||
[2] | soft_rxp_rst: RX PLL soft reset | ||||
[1] | soft_txp_rst: TX PLL soft reset | ||||
[0] | eio_sys_rst: PMA system reset. Set this bit to start the internal reset sequence. | ||||
0x313 |
PHY_PMA_SLOOP |
[3:0] or [9:0] |
Serial PMA loopback. Each bit that is asserted directs the IP core to connect the corresponding TX–RX lane pair on the internal loopback path, by setting the corresponding transceiver in serial loopback mode. This option is not available for CAUI-4 variations. |
0 | RW |
0x314 |
PHY_PCS_INDIRECT_ADDR |
[2:0] | Supports indirect addressing of individual FIFO flags in the 10G PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the PHY_PCS_INDIRECT_DATA register. The value in the PHY_PCS_INDIRECT_ADDR register directs the IP core to make available the following FIFO flag:
|
3'b0 | RW |
0x315 |
PHY_PCS_INDIRECT_DATA |
[3:0] or [9:0] |
PCS indirect data. To read a FIFO flag, set the value in the PHY_PCS_INDIRECT_ADDR register to indicate the flag you want to read. After you set the specific flag indication in the PHY_PCS_INDIRECT_ADDR register, each bit [n] in the PHY_PCS_INDIRECT_DATA register has the value of that FIFO flag for the transceiver channel for lane [n]. This register has four valid bits [3:0] in LL 40GbE IP core variations, and ten valid bits [9:0] in standard LL 100GbE IP core variations. This register is not valid for CAUI-4 variations. |
TX full flags | RO |
0x320 |
PHY_TX_PLL_LOCKED |
[9:0] |
Each bit that is asserted indicates that the corresponding lane TX PLL is locked. | 10'b0 | RO |
0x321 |
PHY_EIOFREQ_LOCKED |
[9:0] |
Each bit that is asserted indicates that the corresponding lane RX CDR PLL is locked. |
10'b0 |
RO RO |
0x322 |
PHY_TX_COREPLL_LOCKED |
[2] | RX PLL is locked. | 3'b0 | RO |
[1] | TX PLL is locked. | ||||
[0] | TX PCS is ready. | ||||
0x323 |
PHY_FRAME_ERROR |
[3:0] or [19:0] |
Each bit that is asserted indicates that the corresponding virtual lane has a frame error. If you read a non-zero value in this register, You can clear these bits with the PHY_SCLR_FRAME_ERROR register. Altera recommends that you set bit [0] of the PHY_SCLR_FRAME_ERROR register and read the PHY_FRAME_ERROR register again to determine if the PHY frame error is generated continuously. These bits are not sticky: the IP core clears them more than once while attempting to achieve alignment. |
0xF or 0xFFFFF |
RO |
0x324 |
PHY_SCLR_FRAME_ERROR | [0] |
Synchronous clear for PHY_FRAME_ERROR register. Write the value of 1 to this register to clear the PHY_FRAME_ERROR register. |
1'b0 |
RW |
0x325 | PHY_EIO_SFTRESET | [1] | Set this bit to clear the RX FIFO. | 2'b00 | RW |
[0] | RX PCS reset: set this bit to reset the RX PCS. | ||||
0x326 |
PHY_RXPCS_STATUS |
[1:0] | Indicates the RX PCS is fully aligned and ready to accept traffic.
|
0 | RO |
0x340 |
PHY_REFCLK_KHZ |
[31:0] | Reference clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The reference clock frequency is the value in the PHY_REFCLK_KHZ register times the frequency of the clk_status clock, divided by 100. | RO | |
0x341 |
PHY_RXCLK_KHZ |
[31:0] | RX clock (clk_rxmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX clock frequency is the value in the PHY_RXCLK_KHZ register times the frequency of the clk_status clock, divided by 100. | RO | |
0x342 |
PHY_TXCLK_KHZ |
[31:0] | TX clock (clk_txmac) frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX clock frequency is the value in the PHY_TXCLK_KHZ register times the frequency of the clk_status clock, divided by 100. | RO | |
0x343 |
PHY_RECCLK_KHZ |
[31:0] | RX recovered clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The RX recovered clock frequency is the value in the PHY_RECCLK_KHZ register times the frequency of the clk_status clock, divided by 100. | RO | |
0x344 |
PHY_TXIOCLK_KHZ |
[31:0] | TX PMA clock frequency in KHz, assuming the clk_status clock has the frequency of 100 MHz. The TX PMA clock frequency is the value in the PHY_TX10CLK_KHZ register times the frequency of the clk_status clock, divided by 100. | RO |