Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

3.4.1.3. LL 40GBASE-KR4 Registers

Most LL 40GBASE-KR4 registers are 10GBASE-KR PHY registers of the Arria 10 10GBASE-KR PHY IP core, documented in the Arria 10 Transceiver PHY User Guide. Exceptions are:

  • The register offsets of the 10GBASE-KR PHY registers are offset by negative 0x400 in the LL 40GBASE-KR4 variations of the LL 40-100GbE IP core. The Arria 10 10GBASE-KR PHY IP core registers begin at offset 0x4B0. In the LL 40GBASE-KR4 IP core, these registers begin at offset 0x0B0.
  • The LL 40GBASE-KR4 variations of the LL 40-100GbE IP core have additional 40GBASE-KR4 related registers and register fields.
  • The FEC error insertion feature requires that you program some Arria 10 device registers through the Arria 10 dynamic reconfiguration interface. The FEC error count is collected in other Arria 10 device registers that you access through the Arria 10 dynamic reconfiguration interface. You access the relevant Arria 10 device registers at offsets 0xBD through 0xE3 for Lane 0, 0x4BD through 0x4E3 for Lane 1, 0x8BD through 0x8E3 for Lane 2, and 0xCBD through 0xCE3 for Lane 3. The descriptions of the LL 40GBASE-KR4 registers that depend on these Arria 10 device registers provide the individual A10 register information.

For your convenience, the LL 40-100GbE IP core user guide includes an appendix with the 10GBASE-KR PHY register descriptions: Arria 10 10GBASE-KR Registers.

Table 39.  LL 40-100GbE IP Core 40GBASE-KR4 Registers and Register Fields Not in Arria 10 10GBASE-KR PHY IP Core

Documents the differences between the Arria 10 10GBASE-KR PHY register definitions and the 40GBASE-KR4 registers of the LL 40-100GbE IP core. All 10GBASE-KR PHY registers and register fields not listed in the table are available in the 40GBASE-KR4 variations of the LL 40-100GbE IP core.

The 10GBASE-KR PHY register listings are available in the 0xB0Arria 10 10GBASE-KR Registers appendix and in the 10GBASE-KR PHY Register Defintions section of the 10GBASE-KR PHY IP Core section in the Arria 10 Transceiver PHY User Guide. The information in these two sources should be identical. Refer to Arria 10 10GBASE-KR Registers for details.

Where the 10GBASE-KR PHY register definitions list 10GBASE-R, substitute 40GBASE-KR4 with auto-negotiation and link training both turned off, and where the 10GBASE-KR PHY register definitions list 10GBASE-KR (except in the description of 0xCB[24:0]), substitute 40GBASE-KR4. Where a register field description in the 10GBASE-KR PHY register definitions refers to link training or FEC in the single-lane 10GBASE-KR PHY IP core, substitute link training or FEC on Lane 0 of the 40GBASE-KR4 IP core variation.

Registers and register bits not described in either location should be considered Reserved.

To modify a field value in any LL 40GBASE-KR4 specific register, whether an underlying 10GBASE-KR PHY IP core register or one of the registers defined in this table, you must perform a read-modify-write operation to ensure you do not modify the values of any other fields in the register.

Address

Name

Bit

Description

HW Reset Value

Access

0x0B0

SEQ Force Mode[3:0] [7:4]

Forces the sequencer to a specific protocol. Must write the Reset SEQ bit (bit [0]) to 1 for the Force to take effect. The following encodings are defined:

  • 0000: No force
  • 0001: GigE mode (unsupported)
  • 0010: XAUI mode (unsupported)
  • 0100: 40GBASE-R4 mode (without auto-negotiation and without link training)
  • 0101: 40GBASE-KR4 mode
  • 1100: 40GBASE-R4 mode with FEC (without auto-negotiation and without link training)
4'b0 RW
Enable Arria 10 Calibration [8] When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured. 1'b1 RW
LT Failure Response [12] When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY will restart LT. 1'b1 in simulation; 1'b0 in hardware RW
Reserved [17] Reserved

Access FEC error indication selection using the Arria 10 dynamic reconfiguration interface. Refer to the descriptions of register 0xB2.

   
Reserved

[19]

Reserved    
0x0B1 SEQ Reconfig Mode[5:0] [13:8] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 40G data mode
  • Bit 11, mode[3]: GigE data mode
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit13, mode[5]: 40G FEC mode
   
FEC Block Lock [23:20]

FEC Block Lock for lanes [3:0]: bit [20] is FEC block lock for lane 0, bit [21] is FEC block lock for lane 1, bit [22] is FEC block lock for lane 2, and bit [23] is FEC block lock for lane 3.

4'b0 RO
0xB2 KR FEC TX Error Insert, Lane 0 11 Writing a 1 inserts one error pulse into the TX FEC for lane 0, depending on the Transcoder and Burst error settings for lane 0.

You must select these settings through the Arria 10 dynamic reconfiguration interface to the Arria 10 device registers before you write a 1 to the KR FEC TX Error Insert, Lane 0 bit. To select these settings for Lane 0, perform a read-modify-write operation sequence at register offset 0xBD.

You select a Transcoder error by setting the transcode_err bit, resetting the burst_err bit, resetting the burst_err_len field, and leaving the remaining bits at their previous values.

You select a Burst error by setting the burst_err bit, specifying the burst error length in the burst_err_len field, resetting the transcode_err bit, and leaving the remaining bits at their previous values.

1'b0 RWSC
RCLR_ERRBLK_CNT, Lane 0 12 Writing a 1 resets the error block counters.Writing a 0 causes counting to resume.

Each lane has a 32-bit corrected error block counter and a 32-bit uncorrected error block counter in the Arria 10 device registers. Refer to Clause 74.8.4.1 and Clause 74.8.4.2 of IEEE Std 802.3ap-2007.

For Lane 0, the corrected error block counter is in the Arria 10 device registers you access through the Arria 10 dynamic reconfiguration interface at offsets 0xDC to 0xDF: blkcnt_corr[31:0] is in {0xDF[7:0],0xDE[7:0],0xDD[7:0],0xDC[7:0]}.

For Lane 0, the uncorrected error block counter is in the Arria 10 device registers you access through the Arria 10 dynamic reconfiguration interface at offsets 0xE0 to 0xE3: blkcnt_uncorr[31:0] is in {0xE3[7:0],0xE2[7:0],0xE1[7:0],0xE0[7:0]}.

  RW
Reserved [31:13] Reserved    

0x0B5

Register 0xB2 refers to Lane 0. This register is the equivalent of register 0xB2 for Lane 1. The relevant FEC error Arria 10 device registers for Lane 1 are at 0x4BD through 0x4E3 (additional offset of 0x400).

RW

0x0B8

This register is the equivalent of register 0xB2 for Lane 2. The relevant FEC error Arria 10 device registers for Lane 2 are at 0x8BD through 0x8E3 (additional offset of 0x800 compared to the Lane 0 device registers).

RW

0x0BB

This register is the equivalent of register 0xB2 for Lane 3. The relevant FEC error Arria 10 device registers for Lane 3 are at 0xCBD through 0xCE3 (additional offset of 0xC00 compared to the Lane 0 device registers).

RW

0x0C0

Override AN Channel Enable [6]

Overrides the auto-negotiation master channel that you set with the Auto-Negotiation Master parameter, setting the new master channel according to the value in register 0xCC[3:0].

While 0x0C0[6] has the value of 1, the channel encoded in 0xCC[3:0] is the master channel. While 0xC0[6] has the value of 0, the master channel is the channel that you set with the Auto-Negotiation Master parameter.

1'b0

RW

0x0C2 KR4 AN Link Ready [5:0] [17:12] Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1. The following encodings are defined:
  • 6'b000000: 1000BASE-KX
  • 6'b000001: 10GBASE-KX4
  • 6'b000100: 10GBASE-KR
  • 6'b001000: 40GBASE-KR4
  • 6'b010000: 40GBASE-CR4
  • 6'b100000: 100GBASE-CR10

The only valid value for the LL 40GBASE-KR4 IP core is 6'b001000: 40GBASE-KR4.

6'b001000 RO

0x0CB

AN LP ADV Tech_A[24:0] [24:0] Received technology ability field bits of Clause 73 Auto Negotiation. The following protocols are defined:
  • A0 1000BASE-KX
  • A1 10GBASE-KX4
  • A2 10GBASE-KR
  • A3 40GBASE-KR4
  • A4 40GBASE-CR4
  • A5 100GBASE-CR10
  • A24:6 are reserved

The only valid value for the LL 40GBASE-KR4 IP core is A3: 40GBASE-KR4..

For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.

25'b0

RO

0x0CC

Override AN Channel Select [3:0]

If you set the value of the Override AN Channel Enable register field (0xC0[6]) to the value of 1, then while 0xC0[6] has the value of 1, the value in this register field (0xCC[3:0])overrides the master channel you set with the Auto-Negotiation Master parameter.

This register field has the following valid values:

  • 4'b0001: Selects Lane 0
  • 4'b0010: Selects Lane 1
  • 4'b0100: Selects Lane 2
  • 4'b1000: Selects Lane 3

All other values are invalid. The new master channel is encoded with one-hot encoding.

4'b0

RW

0x0D0 Reserved [3:2] Reserved    
Ovride LP Coef Enable [16] When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0x0D1 bits [7:4] and bits[7:0] of 0x0D4 through 0x0D7. 1'b0 RW
Ovride Local RX Coef Enable [17] When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x0D1 bits [11:8] and bits[23:16] of 0x0D4 through 0x0D7. 1'b0 RW
Reserved [31:22] Reserved    

0x0D1

Restart Link training, Lane 1 [1]

When set to 1, resets the 40GBASE-KR4 start-up protocol. When set to 0, continues normal operation. This bit self clears. Refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) in IEEE Std 802.3ap-2007.

Register bit 0xD1[0] refers to Lane 0. This bit is the equivalent of register 0xD1[0] for Lane 1.

1'b0

RW SC
Restart Link training, Lane 2 [2]

This bit is the equivalent of register 0xD1[0] for Lane 2.

1'b0

RW SC
Restart Link training, Lane 3 [3]

This bit is the equivalent of register 0xD0[1] for Lane 3.

1'b0

RW SC

0x0D1

Updated TX Coef new, Lane 1 [5]

When set to 1, indicates that new link partner coefficients are available to send. The LT logic starts sending the new values set in 0xD4[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[16] (Ovride LP Coef enable) has the value of 1. If 0xD0[16] has the value of 0, this register field (0xD1[5]) has no effect.

Register bit 0xD1[4] refers to Lane 0. This bit is the equivalent of register 0xD1[4] for Lane 1.

1'b0

RW SC

Updated TX Coef new, Lane 2 [6]

This bit is the equivalent of register 0xD1[5] for Lane 2.

1'b0

RW SC
Updated TX Coef new, Lane 3 [7]

This bit is the equivalent of register 0xD1[5] for Lane 3.

1'b0

RW SC

0x0D1

Updated RX Coef new, Lane 1 [9]

When set to 1, indicates that new local device coefficients are available for Lane 1. The LT logic changes the local TX equalizer coefficients as specified in 0xE1[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1. If 0xD0[17] has the value of 0, this register field (0xD1[9]) has no effect.

Register bit 0xD1[8] refers to Lane 0. This bit is the equivalent of register 0xD1[8] for Lane 1.

1'b0

RW

Updated RX Coef new, Lane 2 [10]

When set to 1, indicates that new local device coefficients are available for Lane 2. The LT logic changes the local TX equalizer coefficients as specified in 0xE5[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1.

This bit is the equivalent of register 0xD1[9] for Lane 2.

1'b0

RW

Updated RX Coef new, Lane 3 [11]

When set to 1, indicates that new local device coefficients are available for lane 3. The LT logic changes the local TX equalizer coefficients as specified in 0xE9[23:16]. When set to 0, continues normal operation. This bit self clears.

This override of normal operation can only occur if 0xD0[17] (Ovride Local RX Coef enable) has the value of 1.

This bit is the equivalent of register 0xD1[9] for Lane 3.

1'b0

RW

0x0D2

Reserved [7:6] Reserved  
[13:8]

Register bits 0xD2[5:0] refer to Lane 0. These bits are the equivalent of 0xD2[5:0] for Lane 1.

For Link Training Frame lock Error, Lane 1, if the tap settings specified by the fields of 0xE2 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

[21:16]

These bits are the equivalent of 0xD2[5:0] for Lane 2.

For Link Training Frame lock Error, Lane 2, if the tap settings specified by the fields of 0xE6 are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

[29:24]

These bits are the equivalent of 0xD2[5:0] for Lane 3.

For Link Training Frame lock Error, Lane 3, if the tap settings specified by the fields of 0xEA are the same as the initial parameter value, the frame lock error was unrecoverable.

RO

0x0D4 LD coefficient update[5:0], Lane 0 [5:0] Reflects the contents of the first 16-bit word of the training frame sent to Lane 0 from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride LP Coef enable control bit (0x0D0 bit [16]), these bits become writeable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

Before you can send these bits, you must enable the override in 0x0D0 bit [16] and also signal a new word in 0x0D1 bit [4].

For more information, refer to bit 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3ap-2007. 		  RO/RW
LP Coefficient Update[5:0], Lane 0 [21:16] Reflects the contents of the first 16-bit word of the training frame most recently received on Lane 0 from the control channel.

Normally the bits in this register are read only; however, when training is disabled by setting low the Link Training enable control bit (bit 0 at offset 0xD0), these bits become writeable. The following fields are defined:

  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

Before you can send these bits, you must enable the override in 0x0D0 bit [17] and also signal a new word in 0x0D2 bit [8].

For more information, refer to bit 10G BASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.

   
0x0D5 Reserved [31:21] Reserved    
0x0D6 LT VODMAX ovrd, Lane 0 [4:0] Override value for the VMAXRULE parameter on Lane 0. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only effects the local device TX output for the channel specified.

This value must be greater than the INITMAINVAL parameter for proper operation. Note this will also override the PREMAINVAL parameter value.

0x1C (28 decimal) for simulation; 0 for compilation RW
  LT VODMAX ovrd Enable, Lane 0 [5] When set to 1, enables the override value for the VMAXRULE parameter stored in the LT VODMAX ovrd, Lane 0 register field. 1 for simulation; 0 for compilation RW
  LT VODMin ovrd, Lane 0 [12:8] Override value for the VODMINRULE parameter on Lane 0. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.

0x19 (25 decimal) for simulaton; 0 for compilation RW
  LT VODMin ovrd Enable, Lane 0 [13] When set to 1, enables the override value for the VODMINRULE parameter stored in the LT VODMin ovrd, Lane 0 register field. 1 for simulation; 0 for compilation RW
  LT VPOST ovrd, Lane 0 [21:16] Override value for the VPOSTRULE parameter on Lane 0. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.

6 for simulation; 0 for compilation RW
  LT VPOST ovrd Enable, Lane 0 [22] When set to 1, enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd, Lane 0 register field. 1 for simulation; 0 for compilation RW
  LT VPre ovrd, Lane 0 [28:24] Override value for the VPRERULE parameter on Lane 0. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPREVAL parameter for proper operation.

4 for simulation; 0 for compilation RW
  LT VPre ovrd Enable, Lane 0 [29] When set to 1, enables the override value for the VPRERULE parameter stored in the LT VPre ovrd, Lane 0 register field. 1 for simulation; 0 for compilation RW

0xE0

Register 0xD3 refers to Lane 0. This register, register 0xE0, is the equivalent of register 0xD3 for Lane 1 link training.

RW

0xE1

Register 0xD4 refers to Lane 0. This register, register 0xE1, is the equivalent of register 0xD4 for Lane 1 link training.

RW

0xE2

Register 0xD5 refers to Lane 0. This register, register 0xE2, is the equivalent of register 0xD5 for Lane 1 link training.

RO

0xE3

Register 0xD6 refers to Lane 0. This register, register 0xE3, is the equivalent of register 0xD6 for Lane 1 link training..

RW

0xE4

This register is the equivalent of register 0xD3 for Lane 2 link training.

RW

0xE5

This register is the equivalent of register 0xD4 for Lane 2 link training.

R / RW

0xE6

This register is the equivalent of register 0xD5 for Lane 2 link training.

RO

0xE7

This register is the equivalent of register 0xD6 for Lane 2 link training.

RW

0xE8

This register is the equivalent of register 0xD3 for Lane 3 link training.

RW

0xE9

This register is the equivalent of register 0xD4 for Lane 3 link training.

R / RW

0xEA

This register is the equivalent of register 0xD5 for Lane 3 link training.

RO

0xEB

This register is the equivalent of register 0xD6 for Lane 3 link training.

RW

Related Information
Level Two Title