Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Document Table of Contents

4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy

For Arria 10 devices, the Quartus® Prime Standard Edition software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a SignalTap® II file with probe points matching your design hierarchy.

The Quartus® Prime software stores these files in the IP core Diretory/synth/debug/stp/ directory.

Synthesize your design using the Quartus® Prime software.
  1. To open the Tcl console, click View > Utility Windows > Tcl Console.
  2. Type the following command in the Tcl console:
    source <IP core Directory>/synth/debug/stp/build_stp.tcl
  3. To generate the STP file, type the following command:
    main -stp_file <output stp file name>.stp -xml_file <input xml_file name>.xml -mode build
  4. To add this SignalTap® II file (.stp) to your project, select Project > Add/Remove Files in Project. Then, compile your design.
  5. To program the FPGA, click Tools > Programmer.
  6. To start the SignalTap® II Logic Analyzer, click Quartus Prime > Tools > SignalTap® II Logic Analyzer.
    The software generation script may not assign the SignalTap® II acquisition clock in <output stp file name>.stp. Consequently, the Quartus® Prime software automatically creates a clock pin called auto_stp_external_clock. You may need to manually substitute the appropriate clock signal as the SignalTap® II sampling clock for each STP instance.
  7. Recompile your design.
  8. To observe the state of your IP core, click Run Analysis.
    You may see signals or SignalTap® II instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances.They are present because software generates wider buses and some instances that your design does not include.