Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Document Table of Contents

2.9.1. Generating the Low Latency 40-100GbE Testbench

A single procedure generates both the testbench and the example project. The procedure varies depending on your target device. To generate the testbench and example project:

  1. Follow the steps in Specifying the Low Latency 40-100GbE IP Core Parameters and Options to parameterize your IP core.
  2. If your IP core variation targets a Stratix V device, go to step 4.
  3. If your IP core variation targets an Arria 10 device, in the Low Latency 40-100GbE parameter editor, click the Generate Example Design button to generate the testbench and example project for the IP core variation you intend to generate.
    Tip: You are prompted to locate the new testbench and example project in the directory <working directory>/alt_eth_ultra_0_example_design. You can accept the default path or modify the path to the new testbench and example project.
  4. Generate the IP core by clicking Generate HDL for Arria 10 variations or Generate for Stratix V variations.
    Note: If your IP core variation targets a Stratix V device, when prompted at the start of generation, you must turn on Generate example design. Turning on Generate example design is the only process that generates a functional testbench and a functional example project for Stratix V variations.

    When the IP core is generated in <working directory>, the testbench and example project are generated in different locations depending on the device family your IP core variation targets.

    • For Stratix V variations, the testbench and example project are generated in <working directory>/<IP core variation>_example_design/alt_eth_ultra.
    • For Arria 10 variations, the testench and the compilation-only and hardware design examples are generated in the directory you specify in Step 2. If you do not modify the location text at the prompt, they are generated in <working directory>/alt_eth_ultra_0_example_design.

The directory with the testbench and design example has four subdirectories for Arria 10 variations and three subdirectories for Stratix V variations:

  • example_testbench
  • compilation_test_design
  • hardware_test_design
  • ex_40g, ex_100g, or ex_100g_caui4, for Arria 10 variations only

The ex_40g, ex_100g, or ex_100g_caui4 directory contains a copy of the IP core variation. The testbench and design examples (compilation-only and hardware design example) for your Arria 10 IP core variation connect to the copy in this directory rather than to the copy you generate in <working directory>.