2.7.3. Transceiver PLL Required in Arria 10 Designs
Low Latency 40-100GbE IP cores that target Arria 10 devices require an external TX transceiver PLL to compile and to function correctly in hardware.
In this example, Use external TX MAC PLL is turned off. Therefore, the TX MAC PLL is in the IP core. If you turn on the Use external TX MAC PLL parameter you must also instantiate and connect a TX MAC PLL outside the LL 40-100GbE IP core.
You can use the IP Catalog to create a transceiver PLL.
- Select Arria 10 Transceiver ATX PLL or Arria 10 Transceiver CMU PLL.
- In the parameter editor, set the following parameter values:
- PLL output frequency to 5156.25 MHz for standard LL 40-100GbE IP core variations or to 12890.625 MHz for CAUI-4 variations. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 or 25.78125 Gbps data rate through the transceiver.
- PLL reference clock frequency to the value you specified for the PHY reference frequency parameter.
When you generate a Low Latency 40-100GbE IP core, the software also generates the HDL code for an ATX PLL, in the file <variation_name> /arria10_atx_pll.v. However, the HDL code for the Low Latency 40-100GbE IP core does not instantiate the ATX PLL. If you choose to use the ATX PLL provided with the Low Latency 40-100GbE IP core, you must instantiate and connect the instances of the ATX PLL with the LL 40-100GbE IP core in user logic.
The number of external PLLs you must generate or instantiate depends on the distribution of your Ethernet TX serial lines across physical transceiver channels and banks. You specify the clock network to which each PLL output connects by setting the clock network in the PLL parameter editor. The example project demonstrates one possible choice, which is compatible with the ATX PLL provided with the LL 40-100GbE IP core.
You must connect the tx_serial_clk input pin for each Low Latency 40-100GbE IP core PHY link to the output port of the same name in the corresponding external PLL. You must connect the pll_locked input pin of the Low Latency 40-100GbE IP core to the logical AND of the pll_locked output signals of the external PLLs for all of the PHY links.
User logic must provide the AND function and connections. Refer to the example project for example working user logic including one correct method to instantiate and connect an external PLL.
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