Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Document Table of Contents

3.4.2. LL 40‑100GbE Hardware Design Example Registers

The following sections describe the registers that are included in the LL 40-100GbE hardware design example and are not a part of the LL 40‑100GbE IP core.