Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Public
Document Table of Contents

3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling

While receiving an incoming packet from the Ethernet link, the LL 40-100GbE IP core expects to detect a terminate character at the end of the packet. When it detects an expected terminate character, the IP core generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control character when it expects a terminate character. The Low Latency 40-100GbE IP core detects and handles the following forms of malformed packets:

  • If the IP core detects an Error character, it generates an EOP, asserts a malformed packet error (rx_error[0] or l<n>_rx_error[0]), and asserts an FCS error (rx_fcs_error (l<n>_rx_fcs_error) and rx_error[1] (l<n>_rx_error[1]). If the IP core subsequently detects a terminate character, it does not generate another EOP indication.
  • If the IP core detects any other control character when it is waiting for an EOP indication (terminate character), the IP core generates an EOP indication (for example, an IDLE or Start character), asserts a malformed packet error (rx_error[0] or l<n>_rx_error[0]), and asserts an FCS error (rx_fcs_error (l<n>_rx_fcs_error) and rx_error[1] (l<n>_rx_error[1]). If the IP core subsequently detects a terminate character, it does not generate another EOP indication.

The IP core ignores a Start control character it receives on any lane other than Lane 0.

When the IP core receives a packet that contains an error deliberately introduced on the Ethernet link using the LL 40-100GbE TX error insertion feature, the IP core identifies it as a malformed packet.