Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Document Table of Contents

1.3.2. Compilation Checking

Altera performs compilation testing on an extensive set of Low Latency 40-100GbE MAC and PHY IP core variations and designs that target different devices, to ensure the Quartus Prime software places and routes the IP core ports correctly.