Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

ID 683628
Date 12/28/2017
Document Table of Contents 40-100GbE IP Core CRC Checking

The 32-bit CRC field is received in the order: X32, X30, . . . X1, and X0 , where X32 is the most significant bit of the FCS field and occupies the least significant bit position in the first FCS byte.

If a CRC32 error is detected, the RX MAC marks the frame invalid by asserting the l<n>_rx_fcs_error and l<n>_rx_fcs_valid (or rx_fcs_error and rx_fcs_valid) signals, as well as the l<n>_rx_error[1] (or rx_error[1]) signal.