Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide

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ID 683628
Date 12/28/2017
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Arria 10 10GBASE-KR Registers B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1 C. Additional Information
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features 1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. Low Latency 40-100GbE IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. Low Latency 40-100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Stratix V Resource Utilization for Low Latency 40-100GbE IP Cores 1.4.2. Arria 10 Resource Utilization for Low Latency 40-100GbE IP Cores
2. Getting Started x
2.1. Installation and Licensing for LL 40-100GbE IP Core for Stratix V Devices 2.2. Licensing IP Cores 2.3. Specifying the Low Latency 40-100GbE IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. Low Latency 40-100GbE IP Core Testbenches 2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches 2.10. Compiling the Full Design and Programming the FPGA 2.11. Initializing the IP Core
2.2. Licensing IP Cores x
2.2.1. OpenCore Plus IP Evaluation
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.5. Clock Requirements for 40GBASE-KR4 Variations 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the Low Latency 40-100GbE IP Core
2.8. Low Latency 40-100GbE IP Core Testbenches x
2.8.1. Low Latency 40-100GbE IP Core Testbench Overview 2.8.2. Understanding the Testbench Behavior
2.9. Simulating the Low Latency 40‑100GbE IP Core With the Testbenches x
2.9.1. Generating the Low Latency 40-100GbE Testbench 2.9.2. Optimizing the Low Latency 40‑100GbE IP Core Simulation With the Testbenches 2.9.3. Simulating with the Modelsim Simulator 2.9.4. Simulating with the NCSim Simulator 2.9.5. Simulating with the VCS Simulator 2.9.6. Testbench Output Example: Low Latency 40-100GbE IP Core
3. Functional Description x
3.1. High Level System Overview 3.2. Low Latency 40-100GbE MAC and PHY Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. Low Latency 40-100GbE MAC and PHY Functional Description x
3.2.1. Low Latency 40-100GbE IP Core TX Datapath 3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces 3.2.3. Low Latency 40-100GbE IP Core RX Datapath 3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Low Latency 40GBASE-KR4 IP Core Variations 3.2.18. Control and Status Interface 3.2.19. Arria 10 Transceiver Reconfiguration Interface 3.2.20. Clocks 3.2.21. Resets
3.2.1. Low Latency 40-100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter‑Packet Gap Generation and Insertion 3.2.1.7. Error Insertion Test and Debug Feature
3.2.2. Low Latency 40-100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.2.2. Low Latency 40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. Low Latency 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. Low Latency 40-100GbE IP Core RX Datapath x
3.2.3.1. Low Latency 40-100GbE IP Core RX Filtering 3.2.3.2. 40-100GbE IP Core Preamble Processing 3.2.3.3. 40-100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. 40-100GbE IP Core CRC Checking 3.2.3.5. LL 40-100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. Pause Ignore 3.2.3.9. Control Frame Identification
3.2.4. Low Latency 40-100GbE IP Core RX Data Bus Interface x
3.2.4.1. Low Latency 40-100GbE IP Core User Interface Data Bus 3.2.4.2. Low Latency 40-100GbE IP Core RX Data Bus 3.2.4.3. Low Latency 40-100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 40-100GbE IP Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. Low Latency 40-100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. Low Latency 40-100GbE IP Core Registers 3.4.2. LL 40‑100GbE Hardware Design Example Registers
3.4.1. Low Latency 40-100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 40GBASE-KR4 Registers 3.4.1.4. Low Latency 40-100GbE IP Core MAC Configuration Registers 3.4.1.5. Pause Registers 3.4.1.6. TX Statistics Registers 3.4.1.7. RX Statistics Registers 3.4.1.8. 1588 PTP Registers
3.4.2. LL 40‑100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a SignalTap II Debug File to Match Your Design Hierarchy
A. Arria 10 10GBASE-KR Registers x
A.1. 10GBASE-KR PHY Register Definitions
C. Additional Information x
C.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Archives C.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision History C.3. How to Contact Altera C.4. Typographic Conventions
1. About the Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Arria 10 10GBASE-KR Registers
B. Differences Between Low Latency 40-100GbE IP Core and 40-100GbE IP Core v15.1
C. Additional Information

A.1. 10GBASE-KR PHY Register Definitions

The Avalon-MM slave interface signals provide access to the control and status registers.

The following table specifies the control and status registers that you can access over the Avalon‑MM PHY management interface. A single address space provides access to all registers.

Note: Unless otherwise indicated, the default value of all registers is 0.
Note: Writing to reserved or undefined register addresses may have undefined side effects.
Table 50.  10GBASE-KR Register Definitions
Word Addr Bit R/W Name Description
0x4B0 0 RW Reset SEQ When set to 1, resets the 10GBASE‑KR sequencer (auto rate detect logic), initiates a PCS reconfiguration, and may restart Auto-Negotiation, Link Training or both if AN and LT are enabled (10GBASE-KR mode). SEQ Force Mode[2:0] forces these modes. This reset self clears.
1 RW Disable AN Timer Auto‑Negotiation disable timer. If disabled ( Disable AN Timer = 1) , AN may get stuck and require software support to remove the ABILITY_DETECT capability if the link partner does not include this feature. In addition, software may have to take the link out of loopback mode if the link is stuck in the ACKNOWLEDGE_DETECT state. To enable this timer set Disable AN Timer = 0.
2 RW Disable LF Timer When set to 1, disables the Link Fail timer. When set to 0, the Link Fault timer is enabled.
3 RW fail_lt_if_ber When set to 1, the last LT measurement is a non-zero number. Treat this as a failed run. 0 = normal.
7:4 RW SEQ Force Mode[3:0]

Forces the sequencer to a specific protocol. Must write the Reset SEQ bit to 1 for the Force to take effect. The following encodings are defined:

  • 0000: No force
  • 0001: GigE
  • 0010: XAUI
  • 0100: 10GBASE-R
  • 0101: 10GBASE-KR
  • 1100: 10GBASE-KR FEC
8 RW Enable Arria 10 Calibration When set to 1, it enables the Arria 10 HSSI reconfiguration calibration as part of the PCS dynamic reconfiguration. 0 skips the calibration when the PCS is reconfigured.
11:9 RW Reserved —
12 RW LT failure response When set to 1, LT failure causes the PHY to go into data mode. When set to 0, LT failure restarts auto-negotiation (if enabled). If auto-negotiation is not enabled, the PHY will restart LT.
0x4B0 16 RW KR FEC enable 171.0 When set to 1, FEC is enabled. When set to 0, FEC is disabled. Resets to the CAPABLE_FEC parameter value.
17 RW KR FEC enable err ind 171.1 When set to 1, KR PHY FEC decoding errors are signaled to the PCS. When set to 0, FEC errors are not signaled to the PCS. See Clause 74.8.3 of IEEE 802.3ap-2007 for details.
18 RW KR FEC request When set to 1, enables the FEC request. When this bit changes, you must assert the Reset SEQ bit (0x4B0[0]) to renegotiate with the new value. When set to 0, disables the FEC request.
0x4B1 0 R SEQ Link Ready When asserted, the sequencer is indicating that the link is ready.
1 R SEQ AN timeout When asserted, the sequencer has had an Auto Negotiation timeout. This bit is latched and is reset when the sequencer restarts Auto Negotiation.
2 R SEQ LT timeout When set, indicates that the Sequencer has had a timeout.
13:8 R SEQ Reconfig Mode[5:0] Specifies the Sequencer mode for PCS reconfiguration. The following modes are defined:
  • Bit 8, mode[0]: AN mode
  • Bit 9, mode[1]: LT Mode
  • Bit 10, mode[2]: 10G data mode
  • Bit 11, mode[3]: Gige data mode
  • Bit 12, mode[4]: Reserved for XAUI
  • Bit 13, mode[5]: 10G FEC mode
16 R KR FEC ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY supports FEC. Set as parameter SYNTH_FEC. For more information, refer to Clause 45.2.1.84 of IEEE 802.3ap-2007.
17 R KR FEC err ind ability 170.0 When set to 1, indicates that the 10GBASE-KR PHY is capable of reporting FEC decoding errors to the PCS. For more information, refer to Clause 74.8.3 of IEEE 802.3ap-2007.
0x4B2 0:10 — Reserved —
11 RW KR FEC TX Error Insert Writing a 1 inserts one error pulse into the TX FEC depending on the Transcoder and Burst error settings. This bit self clears.
31:12 — Reserved —
0x4B5 to 0x4BF     Reserved for 40G KR Intentionally left empty for address compatibility with 40G MAC + PHY KR solutions.
0x4C0 0 RW AN enable When set to 1, enables Auto Negotiation function. The default value is 1. For additional information, refer to 7.0.12 in Clause 73.8 Management Register Requirements, of IEEE 802.3ap-2007.
1 RW AN base pages ctrl When set to 1, the user base pages are enabled. You can send any arbitrary data via the user base page low/high bits. When set to 0, the user base pages are disabled and the state machine generates the base pages to send.
2 RW AN next pages ctrl When set to 1, the user next pages are enabled. You can send any arbitrary data via the user next page low/high bits. When set to 0, the user next pages are disabled. The state machine generates the null message to send as next pages.
3 RW Local device remote fault When set to 1, the local device signals Remote Faults in the Auto Negotiation pages. When set to 0, a fault has not occurred.
4 RW Force TX nonce value When set to 1, forces the TX nonce value to support some UNH testing modes. When set to 0, this is normal operation.
5 RW Override AN Parameters Enable When set to 1, overrides the AN_TECH, AN_FEC, and AN_PAUSE parameters and uses the bits in 0xC3 instead. You must reset the Sequencer to reconfigure and restart into Auto Negotiation mode. When set to 0, this is normal operation and is used with 0x4B0 bit 0 and 0x4C3 bits[30:16].
0x4C1 0 RW Reset AN When set to 1, resets all the 10GBASE-KR Auto Negotiation state machines. This bit is self-clearing.
4 RW Restart AN TX SM When set to 1, restarts the 10GBASE-KR TX state machine. This bit self clears. This bit is active only when the TX state machine is in the Auto Negotiation state. For more information, refer to 7.0.9 in Clause 73.8 Management Register Requirements of IEEE 802.3ap-2007.
8 RW AN Next Page When asserted, new next page info is ready to send. The data is in the XNP TX registers. When 0, the TX interface sends null pages. This bit self clears. Next Page (NP) is encoded in bit D15 of Link Codeword. For more information, refer to Clause 73.6.9 and 7.16.15 of Clause 45.2.7.6 of IEEE 802.3ap-2007.
0x4C2 1 RO AN page received When set to 1, a page has been received. When 0, a page has not been received. The current value clears when the register is read. For more information, refer to 7.1.6 in Clause 73.8 of IEEE 802.3ap-2007.
2 RO AN Complete When asserted, Auto‑Negotiation has completed. When 0, Auto Negotiation is in progress. For more information, refer to 7.1.5 in Clause 73.8 of IEEE 802.3ap-2007.
3 RO AN ADV Remote Fault When set to 1, fault information has been sent to the link partner. When 0, a fault has not occurred. The current value clears when the register is read. Remote Fault (RF) is encoded in bit D13 of the base Link Codeword. For more information, refer to Clause 73.6.7 of and 7.16.13 of IEEE 802.3ap‑2007.
4 RO AN RX SM Idle When set to 1, the Auto‑Negotiation state machine is in the idle state. Incoming data is not Clause 73 compatible. When 0, the Auto‑Negotiation is in progress.
5 RO AN Ability When set to 1, the transceiver PHY is able to perform Auto Negotiation. When set to 0, the transceiver PHY i s not able to perform Auto Negotiation. If your variant includes Auto Negotiation, this bit is tied to 1. For more information, refer to 7.1.3 and 7.48.0 of Clause 45 of IEEE 802.3ap-2007.
6 RO AN Status When set to 1, link is up. When 0, the link is down. The current value clears when the register is read. For more information, refer to 7.1.2 of Clause 45 of IEEE 802.3ap-2007.
7 RO LP AN Ability When set to 1, the link partner is able to perform Auto Negotiation. When 0, the link partner is not able to perform Auto-Negotiation. For more information, refer to 7.1.0 of Clause 45 of IEEE 802.3ap-2007.
0x4C2 8 RO FEC negotiated – enable FEC from SEQ When set to 1, PHY is negotiated to perform FEC. When set to 0, PHY is not negotiated to perform FEC.
9 RO Seq AN Failure When set to 1, a sequencer Auto Negotiation failure has been detected. When set to 0, an Auto Negotiation failure has not been detected.
17:12 RO KR AN Link Ready[5:0] Provides a one-hot encoding of an_receive_idle = true and link status for the supported link as described in Clause 73.10.1. The following encodings are defined:
  • 6'b000000: 1000BASE-KX
  • 6'b000001: 10GBASE-KX4
  • 6'b000100: 10GBASE-KR
  • 6'b001000: 40GBASE-KR4
  • 6'b010000: 40GBASE-CR4
  • 6'b100000: 100GBASE-CR10
0x4C3 15:0 RW User base page low The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages ctrl bit is set. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK which is controlled by the SM
  • [13]: Remote Fault bit
  • [12:10]: Pause bits
  • [9:5]: Echoed nonce which are set by the state machine
  • [4:0]: Selector
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
21:16 RW Override AN_TECH[5:0]

AN_TECH value with which to override the current value. The following bits are defined:

  • Bit-16 = AN_TECH[0]= 1000BASE-KX
  • Bit-17 = AN_TECH[1] = XAUI
  • Bit-18 = AN_TECH[2] = 10GBASE-KR
  • Bit-19 = AN_TECH[3] = 40G
  • Bit-20 = AN_TECH[4] = CR-4
  • Bit-21 = AN_TECH[5] = 100G
You must set 0x4C0 bit-5 for this to take effect .
25:24 RW Override AN_FEC[1:0] AN_FEC value with which to override the current value. The following bits are defined:
  • Bit-24 = AN_ FEC [0] = Capability
  • Bit-25 = AN_ FEC [1] = Request
You must set 0x4C0 bit-5 for this to take effect.
30:28 RW Override AN_PAUSE[2:0] AN_PAUSE value with which to override the current value. The following bits are defined:
  • Bit-28 = AN_PAUSE [0] = Pause Ability
  • Bit-29 = AN_PAUSE [1] = Asymmetric Direction
  • Bit-30 = AN_PAUSE [2] = Reserved
You must set 0x4C0 bit-5 for this to take effect.
0x4C4 31:0 RW User base page high The Auto Negotiation TX state machine uses these bits if the Auto Negotiation base pages ctrl bit is set. The following bits are defined:
  • [29:5]: Correspond to page bits 45:21 which are the technology ability.
  • [4:0]: Correspond to bits 20:16 which are TX nonce bits.
Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
0x4C5 15:0 RW User Next page low The Auto Negotiation TX state machine uses these bits if the AN Next Page control bit is set. The following bits are defined:
  • [15]: next page bit
  • [14]: ACK controlled by the state machine
  • [13]: Message Page (MP) bit
  • [12]: ACK2 bit
  • [11]: Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007. Bit 49, the PRBS bit, is generated by the Auto‑Negotiation TX state machine.
0x4C6 31:0 RW User Next page high The Auto Negotiation TX state machine uses these bits if the Auto Negotiation next pages ctrl bit is set. Bits [31:0] correspond to page bits [47:16]. Bit 49, the PRBS bit, is generated by the Auto Negotiation TX state machine.
0x4C7 15:0 RO LP base page low The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [15] Next page bit
  • [14] ACK which is controlled by the state machine
  • [13] RF bit
  • [12:10] Pause bits
  • [9:5] Echoed Nonce which are set by the state machine
  • [4:0] Selector
0x4C8 31:0 RO LP base page high The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [31:30]: Reserved
  • [29:5]: Correspond to page bits [45:21] which are the technology ability
  • [4:0]: Correspond to bits [20:16] which are TX Nonce bits
0x4C9 15:0 RO LP Next page low The AN RX state machine receives these bits from the link partner. The following bits are defined:
  • [15]: Next page bit
  • [14]: ACK which is controlled by the state machine
  • [13]: MP bit
  • [12] ACK2 bit
  • [11] Toggle bit
For more information, refer to Clause 73.7.7.1 Next Page encodings of IEEE 802.3ap-2007.
0x4CA 31:0 RO LP Next page high The AN RX state machine receives these bits from the link partner. Bits [31:0] correspond to page bits [47:16]
0x4CB 24:0 RO AN LP ADV Tech_A[24:0] Received technology ability field bits of Clause 73 Auto Negotiation. The 10GBASE‑KR PHY supports A0 and A2. The following protocols are defined:
  • A0 1000BASE-KX
  • A1 10GBASE-KX4
  • A2 10GBASE-KR
  • A3 40GBASE-KR4
  • A4 40GBASE-CR4
  • A5 100GBASE-CR10
  • A24:6 are reserved
For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
26:25 RO AN LP ADV FEC_F[1:0] Received FEC ability bits FEC (F0:F1) is encoded in bits D46:D47 of the base Link Codeword. F0 is FEC ability. F1 is FEC requested. See Clause 73.6.5 of IEEE 802.3ap-2007 for details.
27 RO AN LP ADV Remote Fault Received Remote Fault (RF) ability bits. RF is encoded in bit D13 of the base link codeword in Clause 73 AN. For more information, refer to Clause 73.6.7 of IEEE 802.3ap‑2007.
30:28 RO AN LP ADV Pause Ability_C[2:0] Received pause ability bits. Pause (C0:C1) is encoded in bits D11:D10 of the base link codeword in Clause 73 AN as follows:
  • C0 is the same as PAUSE as defined in Annex 28B
  • C1 is the same as ASM_DIR as defined in Annex 28B
  • C2 is reserved
0x4D0 0 RW Link Training enable When 1, enables the 10GBASE-KR start-up protocol. When 0, disables the 10GBASE-KR start-up protocol. The default value is 1. For more information, refer to Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.1) of IEEE 802.3ap‑2007.
1 RW dis_max_wait_tmr When set to 1, disables the LT max_wait_timer. Used for characterization mode when setting much longer BER timer values. The default value is 0.
2 RW Reserved Reserved
3 RW Reserved Reserved
7:4 RW main_step_cnt [3:0] Specifies the number of equalization steps for each main tap update. There are about 20 settings for the internal algorithm to test. The valid range is 1-15. The default value is 4'b0001.
11:8 RW prepost_step_cnt [3:0] Specifies the number of equalization steps for each pre- and post-tap update. From 16-31 steps are possible. The default value is 4'b0001.
0x4D0 14:12 RW equal_cnt [2:0]

Adds hysteresis to the error count to avoid local minimums. The following values are defined:

  • 000 = 0
  • 001 = 2
  • 010 = 4
  • 011 = 8
  • 100 = 16
  • 101 = 32
  • 110 = 64
  • 111 = 128
The default value is 101.
15 RW disable Initialize PMA on max_wait_timeout When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not initialized upon entry into the Training_Failure state. This happens when max_wait_timer_done, which sets training_failure = true (reg 0xD2 bit 3). Used for UNH testing. When set to 0, PMA values are initialized upon entry into Training_Failure state. Refer to Figure 72-5 of IEEE 802.3ap-2007 for more details. The default value is 0.
16 RW Ovride LP Coef enable When set to 1, overrides the link partner's equalization coefficients; software changes the update commands sent to the link partner TX equalizer coefficients. When set to 0, uses the Link Training logic to determine the link partner coefficients. Used with 0x4D1 bit-4 and 0x4D4 bits[7:0]. The default value is 0.
17 RW Ovride Local RX Coef enable When set to 1, overrides the local device equalization coefficients generation protocol. When set, the software changes the local TX equalizer coefficients. When set to 0, uses the update command received from the link partner to determine local device coefficients. Used with 0x4D1 bit-8 and 0x4D4 bits[23:16]. The default value is 0.
0x4D0 18 RW VOD Training Enable

Defines whether or not to skip adjustment of the link partner’s VOD (main tap) during link training. The following values are defined:

  • 1 = Exercise VOD (main tap) adjustment during link training
  • 0 = Skip VOD (main tap) adjustment during link training

The default value is 0.
19 RW Bypass DFE

Defines whether or not Decision Feedback Equalization (DFE) is enabled at the end of link training. The following values are defined:

  • 1 = Bypass continuous adaptive DFE at the end of link training
  • 0 = Enable continuous adaptive DFE at the end of link training

The default value for simulation is 1. The default value for hardware is 0.

21:20 RW dfe_freeze_mode

Defines the behavior of DFE taps at the end of link training

  • 00 = do not freeze any DFE taps
  • 01 = Freeze all DFE taps
  • 10 = reserved
  • 11 = reserved
The default value is 01.
Note: These bits will be effective only when bit [19] is set to 0.
0x4D0 22 RW adp_ctle_vga_mode

Defines whether or not CTLE/VGA adaptation is in adaptive or manual mode. The following values are defined:

  • 0 = CTLE sweep before start of TX-EQ during link training.
  • 1 = manual CTLE mode. Link training algorithm sets fixed CTLE value, as specified in bits [28:24]. The default value is 1 for simulation. .

The default value is 0 for hardware.

28:24 RW Manual CTLE

Defines the CTLE value used by the link training algorithm when in manual CTLE mode. These bits are only effective when 0x4D0[22] is set to 1.

The default value is 1.
31:29 RW Manual VGA

Defines the VGA value used by the link training algorithm when in manual VGA mode. These bits are only effective when 0x4D0[22] is set to 1.

The default value is 4 for simulation. The default value is 7 for hardware.

0x4D1 0 RW Restart Link training When set to 1, resets the 10GBASE-KR start-up protocol. When set to 0, continues normal operation. This bit self clears. For more information, refer to the state variable mr_restart_training as defined in Clause 72.6.10.3.1 and 10GBASE-KR PMD control register bit (1.150.0) IEEE 802.3ap‑2007.
4 RW Updated TX Coef new When set to 1, there are new link partner coefficients available to send. The LT logic starts sending the new values set in 0x4D4 bits[7:0] to the remote device. When set to 0, continues normal operation. This bit self clears. Must enable this override in 0x4D0 bit16.
8 RW Updated RX coef new When set to 1, new local device coefficients are available. The LT logic changes the local TX equalizer coefficients as specified in 0x4D4 bits[23:16]. When set to 0, continues normal operation. This bit self clears. Must enable the override in 0x4D0 bit17.
21:20 RW Reserved Reserved
0x4D2 0 RO Link Trained - Receiver status When set to 1, the receiver is trained and is ready to receive data. When set to 0, receiver training is in progress. For more information, refer to the state variable rx_trained as defined in Clause 72.6.10.3.1 of IEEE 802.3ap‑2007.
1 RO Link Training Frame lock When set to 1, the training frame delineation has been detected. When set to 0, the training frame delineation has not been detected. For more information, refer to the state variable frame_lock as defined in Clause 72.6.10.3.1 of IEEE 802.3ap‑2007.
2 RO Link Training Start-up protocol status When set to 1, the start-up protocol is in progress. When set to 0, start-up protocol has completed. For more information, refer to the state training as defined in Clause 72.6.10.3.1 of IEEE 802.3ap‑2007.
3 RO Link Training failure When set to 1, a training failure has been detected. When set to 0, a training failure has not been detected For more information, refer to the state variable training_failure as defined in Clause 72.6.10.3.1 of IEEE 802.3ap‑2007.
4 RO Link Training Error When set to 1, excessive errors occurred during Link Training. When set to 0, the BER is acceptable.
5 RO Link Training Frame lock Error When set to 1, indicates a frame lock was lost during Link Training. If the tap settings specified by the fields of 0x4D5 are the same as the initial parameter value, the frame lock error was unrecoverable.
6 RO RXEQ Frame Lock Loss Frame lock not detected at some point during RXEQ, possibly triggering conditional RXEQ mode.
7 RO CTLE Fine-grained Tuning Error Could not determine the best CTLE due to maximum BER limit at each step in the Fine-grained Tuning mode.
0x4D3 9:0 RW ber_time_frames Specifies the number of training frames to examine for bit errors on the link for each step of the equalization settings. Used only when ber_time_k_frames is 0.The following values are defined:
  • A value of 2 is about 103 bytes
  • A value of 20 is about 104 bytes
  • A value of 200 is about 105 bytes
The default value for simulation is 2'b11. The default value for hardware is 0.
19:10 RW ber_time_k_frames Specifies the number of thousands of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_m_frames = 0 for time/bits to match the following values:
  • A value of 3 is about 107 bits = about 1.3 ms
  • A value of 25 is about 108 bits = about 11ms
  • A value of 250 is about 109 bits = about 11 0ms
The default value for simulation is 0. The default value for hardware is 0xF.
29:20 RW ber_time_m_frames Specifies the number of millions of training frames to examine for bit errors on the link for each step of the equalization settings. Set ber_time_k_frames = 4'd1000 = 0x43E8 for time/bits to match the following values:
  • A value of 3 is about 1010 bits = about 1.3 seconds
  • A value of 25 is about 10 11 bits = about 11 seconds
  • A value of 250 is about 1012 bits = about 110 seconds
0x4D4 5:0 RO or RW LD coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame sent from the local device control channel. Normally, the bits in this register are read-only; however, when you override training by setting the Ovride Coef enable control bit, these bits become writeable. The following fields are defined:
  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3ap-2007.
6 RO or RW LD Initialize Coefficients When set to 1, requests the link partner coefficients be set to configure the TX equalizer to its INITIALIZE state. When set to 0, continues normal operation. For more information, refer to 10G BASE-KR LD coefficient update register bits (1.154.12) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
7 RO or RW LD Preset Coefficients When set to 1, requests the link partner coefficients be set to a state where equalization is turned off. When set to 0 the link operates normally. For more information, refer to 10G BASE-KR LD coefficient update register bit (1.154.13) in Clause 45.2.1.80.3 and Clause 72.6.10.2.3.2 of IEEE 802.3ap-2007.
0x4D4 13:8 RO LD coefficient status[5:0] Status report register for the contents of the second, 16-bit word of the training frame most recently sent from the local device control channel. The following fields are defined:
  • [5:4]: Coefficient (post-tap)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • [1:0]: Coefficient (pre-tap) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LD status report register bit (1.155.5:0) in Clause 45.2.1.81 of IEEE 802.3ap-2007.
14 RO Link Training ready - LD Receiver ready When set to 1, the local device receiver has determined that training is complete and is prepared to receive data. When set to 0, the local device receiver is requesting that training continue. Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to 10G BASE-KR LD status report register bit (1.155.15) in Clause 45.2.1.81 of IEEE 802.3ap-2007.
0x4D4 21:16 RO or RW LP coefficient update[5:0] Reflects the contents of the first 16-bit word of the training frame most recently received from the control channel.

Normally the bits in this register are read only; however, when training is disabled by setting low the KR Training enable control bit, these bits become writeable. The following fields are defined:

  • [5: 4]: Coefficient (+1) update
    • 2'b11: Reserved
    • 2'b01: Increment
    • 2'b10: Decrement
    • 2'b00: Hold
  • [3:2]: Coefficient (0) update (same encoding as [5:4])
  • [1:0]: Coefficient (-1) update (same encoding as [5:4])

For more information, refer to 10G BASE-KR LP coefficient update register bits (1.152.5:0) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.

22 RO or RW LP Initialize Coefficients When set to 1, the local device transmit equalizer coefficients are set to the INITIALIZE state. When set to 0, normal operation continues. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to 10G BASE-KR LP coefficient update register bits (1.152.12) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
23 RO or RW LP Preset Coefficients When set to 1, the local device TX coefficients are set to a state where equalization is turned off. Preset coefficients are used. When set to 0, the local device operates normally. The function and values of the preset bit are defined in 72.6.10.2.3.1. The function and values of the initialize bit are defined in Clause 72.6.10.2.3.2. For more information, refer to 10G BASE-KR LP coefficient update register bits (1.152.13) in Clause 45.2.1.78.3 of IEEE 802.3ap-2007.
0x4D4 29:24 RO LP coefficient status[5:0] Status report register reflects the contents of the second, 16-bit word of the training frame most recently received from the control channel: The following fields are defined:
  • [5:4]: Coefficient (+1)
    • 2'b11: Maximum
    • 2'b01: Minimum
    • 2'b10: Updated
    • 2'b00: Not updated
  • [3:2]: Coefficient (0) (same encoding as [5:4])
  • n [1:0]: Coefficient (-1) (same encoding as [5:4])
For more information, refer to 10G BASE-KR LP status report register bits (1.153.5:0) in Clause 45.2.1.79 of IEEE 802.3ap-2007.
30 RO LP Receiver ready When set to 1, the link partner receiver has determined that training is complete and is prepared to receive data. When set to 0, the link partner receiver is requesting that training continue.

Values for the receiver ready bit are defined in Clause 72.6.10.2.4.4. For more information, refer to 10G BASE-KR LP status report register bits (1.153.15) in Clause 45.2.1.79 of IEEE 802.3ap-2007.

0x4D5 4:0 R LT VOD setting Stores the most recent TX VOD setting trained by the link partner's RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine‑tune the TX preemphasis taps.
13:8 R LT Post-tap setting Stores the most recent TX post-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
20:16 R LT Pre-tap setting Store the most recent TX pre-tap setting trained by the link partner’s RX based on the LT coefficient update logic driven by Clause 72. It reflects Link Partner commands to fine‑tune the TX pre‑emphasis taps.
0x4D5 27:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfig bundle during RX equalization.
29:28 R RXEQ CTLE Mode Most recent ctle_mode setting sent to the reconfig bundle during RX equalization.
31:30 R RXEQ DFE Mode Most recent dfe_mode setting sent tothe reconfig bundle during RX equalization.
0x4D6 4:0 RW LT VODMAX ovrd Override value for the VMAXRULE parameter. When enabled, this value substitutes for the VMAXRULE to allow channel-by-channel override of the device settings. This only affects the local device TX output for the channel specified.

This value must be greater than the INITMAINVAL parameter for proper operation. Note this will also override the PREMAINVAL parameter value.

5 RW LT VODMAX ovrd Enable When set to 1, enables the override value for the VMAXRULE parameter stored in the LT VODMAX ovrd register field.
12:8 RW LT VODMin ovrd Override value for the VODMINRULE parameter. When enabled, this value substitutes for the VMINRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be less than the INITMAINVAL parameter and greater than the VMINRULE parameter for proper operation.

13 RW LT VODMin ovrd Enable When set to 1, enables the override value for the VODMINRULE parameter stored in the LT VODMin ovrd register field.
21:16 RW LT VPOST ovrd Override value for the VPOSTRULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPOSTVAL parameter for proper operation.

22 RW LT VPOST ovrd Enable When set to 1, enables the override value for the VPOSTRULE parameter stored in the LT VPOST ovrd register field.
28:24 RW LT VPre ovrd Override value for the VPRERULE parameter. When enabled, this value substitutes for the VPOSTRULE to allow channel-by-channel override of the device settings. This override only effects the local device TX output for this channel.

The value to be substituted must be greater than the INITPREVAL parameter for proper operation.

29 RW LT VPre ovrd Enable When set to 1, enables the override value for the VPRERULE parameter stored in the LT VPre ovrd register field.
0x4D6 to 0x4FF     Reserved for 40G KR Left empty for address compatibility with 40G MAC+PHY KR solution.
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