220.127.116.11. Main Link RX
You may add an RX repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to clean up jitter and compensate for losses. AC-coupling is optional for Main Link RX.
|FPGA Transceiver PHY Operations||Description|
|Transceiver RX On-Chip Termination||
By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_RX).
|RX Repeater (Redriver or Retimer)||
To clean up jitter and compensate for signal losses, a sink device uses a redriver or retimer between the external DisplayPort connector and the FPGA RX. In such systems, the device places the repeater close to the external DisplayPort connector and regenerates the received DisplayPort signals.
Refer to Table 8 for more information.
|Device Family||VESA DisplayPort Standard version 1.2a Rates (RBR, HBR, HBR2)||VESA DisplayPort Standard version 1.4 Rate (HBR3)||Example Repeater|
|Intel® Stratix® 10 L-tile and H-tile||Not Required 3||Not Required 3||–|
|Intel® Arria® 10 and Intel® Cyclone® 10 GX||Not Required 3||Required 4||
|Arria V||Required 4||Not Applicable 5||TI SN75DP130 (Redriver)|
|Cyclone V||Required 4||Not Applicable 5||TI SN75DP130 (Redriver)|
|Stratix V||Not Required||Not Applicable 5||–|
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