AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

ID 683623
Date 4/13/2020

1.1.3. DisplayPort Hot Plug Detect (HPD)

The DisplayPort sink device drives the HPD signal using 3.3V TTL signal level. The upstream DisplayPort source device monitors the HPD signal.

To prevent the HPD signal from floating when not connected, tie to GND with a >100K ohm resistor in both the DisplayPort Intel® FPGA IP source and sink devices.

Note: The voltage level of the HPD pin uses 3.3 V TTL. FPGA I/Os that are not tolerant with 3.3V TTL require a level shifter.