AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.5. Bitec DisplayPort Daughter Card Revisions

The schematic diagrams of the Bitec HSMC and FMC DisplayPort daughter cards show the connectivity for Intel FPGA development boards.

Table 12.  Bitec DisplayPort FMC Daughter Card Revisions
Revision Release Date Change Note
Rev. 11 August 2018 Added MCD6000C1 Retimer at RX.
  • RX lane polarity inverted
  • RX lane order reversed
  • TX lane polarity not inverted
  • TX lane order not reversed
Rev. 10 May 2017 Added Parade Technologies Retimer (PS8460) on RX.
  • RX lane polarity inverted
  • RX lane order not reversed
  • TX lane polarity not inverted
  • TX lane order not reversed

VESA DisplayPort PHY CTS version 1.4 passed in Intel® Arria® 10 device.

Note: The production of Bitec FMC daughter card Rev. 10 has been discontinued. However, Intel still supports the daughter card to be used with DisplayPort Intel® FPGA IP designs.
Rev. 8 November 2017 –
  • RX lane polarity not inverted
  • RX lane order not reversed
  • TX lane polarity inverted
  • TX lane order reversed
  • No redriver/retimer used
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