AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.2. AUX Channel

The DisplayPort AUX channel is a half-duplex, bidirectional channel running at 1 Mbps rate.
Figure 3. AUX Channel Differential PairThe AUX channel is a differential pair doubly-terminated with 50 ohm resistors and AC-coupled at both source and sink devices.

The 100-KΩ and 1-MΩ pull-up and pull-down resistors are placed between the connectors and AC-coupling capacitors. These resistors help detect any DisplayPort upstream devices, including a powered DisplayPort upstream device by a sink device.

Table 10.  AUX Channel Electrical SpecificationThe table shows the parameters of the DisplayPort AUX channel electrical specification.
Parameter Minimum Maximum Notes
AUX Direct Current (DC) Common Mode Voltage 0.0 V 2.0 V Common mode voltage is equal to Vbias_TX (or Vbias_RX)
AUX Peak-to-Peak Voltage 0.29 V 1.38 V Differential peak-to-peak voltage swing
AUX AC-Coupling Capacitor 75 nF 200 nF The AUX channel AC-coupling capacitors are placed on both the DisplayPort upstream and downstream devices.

Section Content
Implementing Bus LVDS I/O Interface
Implementing Bidirectional LVDS
Detection of DisplayPort Upstream Source Device

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