184.108.40.206. Main Link TX
The FPGA Transceiver PHY TX includes on-chip 100 ohm differential termination and bias voltage generation. You may add a repeater such as a retimer or a redriver in between the FPGA and the external DisplayPort connector to compensate for loss.
|FPGA Transceiver PHY Operations||Description|
|Transceiver PHY TX Reference Clock Connection||
A free-running 135 MHz differential clock (e.g. LVDS) is AC-coupled to a dedicated reference clock input of the transceiver bank. The reference clock input supports on-chip termination (OCT).
Enable OCT using a QSF assignment:
Note: Your design does not require external termination if OCT is enabled.
|Transceiver TX On-Chip Termination||
By default, the Intel® Quartus® Prime software enables differential 100 ohm OCT and bias voltage generation. Your design does not require external 50 ohm termination and bias voltage (Vbias_TX).
|Transceiver TX Channel Bonding||
Bonding TX channels reduces on-chip channel-to-channel skew, which allows more skew margin at the board or system level to meet the DisplayPort Intel® FPGA IP Source inter-lane skew requirement.
Refer to Table 2 for more information.
|Transceiver TX Voltage Swing and Pre-emphasis||
DisplayPort TX specification for the Main Link allows four differential peak-to-peak voltage swing levels, and four pre-emphasis (Post Cursor1) levels. Certain combinations of voltage swing levels and pre-emphasis levels that result in differential peak-to-peak swing outside the allowable range (1.38 V) are not allowed.
The reconfiguration management module available in the Intel® Quartus® Prime design example includes a sub-module that translates the DisplayPort voltage swing and pre-emphasis levels to the FPGA transceiver setting. Refer to Table 3 for more information.
Use the reconfiguration management file and a sub-module of the Intel® Quartus® Prime design examples that maps the DisplayPort levels to the transceiver analog parameter setting.
|TX Repeater (Redriver or Retimer)||
To mitigate system signal losses, you may place a redriver or retimer between the FPGA and the external DisplayPort connector for a box-to-box connection. In such designs, place the repeater close to the external DisplayPort connector and generate the DisplayPort signals at the voltage and pre-emphasis levels determined during link training, instead of the FPGA.
In this case, you can turn off the Support analog reconfiguration option in the DisplayPort Intel® FPGA IP parameter editor and set the FPGA voltage swing in the QSF assignments. The selection of the appropriate signaling level between the FPGA and the repeater depend on the PCB loss and the equalization of the redriver/retimer input. The typical setting for the transmitter is 400 mV voltage swing without pre-emphasis.
Refer to Table 4 for more information.
Bonded TX channels placed in a single transceiver bank results in lower channel-to-channel skew, allowing more skew budget at the board level. For information about the maximum channel-to-channel skew, refer to the Device Datasheet.
You have the option to select bonding mode through the Transceiver PHY parameter editor.
|Device Family||Transceiver PHY Bonding Mode||Notes|
|Intel® Stratix® 10 L-tile and H-tile/ Intel® Arria® 10/ Intel® Cyclone® 10 GX||PMA and PCS bonding||
Note: The digital reset signal (tx_digitalreset) to all TX channels within a bonded group must meet a maximum skew tolerance of one-half the TX parallel clock cycle (tx_clkout). Refer to the Timing Constraints for Bonded PCS and PMA Channels section of the respective Transceiver PHY User Guides for more information.
|Voltage Swing Level||Pre-Emphasis Level|
|2||Supported||Supported||Not allowed||Not allowed|
|3||Supported||Not allowed||Not allowed||Not allowed|
|Device Family||DisplayPort version 1.2 Rates (RBR, HBR, HBR2)||DisplayPort version 1.4 Rate (HBR3)||Example Repeater|
|Intel® Stratix® 10 L-tile and H-tile||Not Required||Not Required||–|
|Intel® Arria® 10||Not Required||Not Required||–|
|Intel® Cyclone® 10 GX||Not Required||Not Required||–|
|Arria V||Required 1||Not Applicable 2||TI SN75DP130 (Redriver)|
|Cyclone V||Required 1||Not Applicable 2||TI SN75DP130 (Redriver)|
|Stratix V||Not Required||Not Applicable 2||–|
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