- Updated the Main Link TX and Main Link RX sections to update the existing information and include information about Intel® Stratix® 10 L-tile and H-tile devices.
- Updated the Implementing Bus LVDS I/O Interface section to include the latest I/O standard information.
- Updated the Bitec DisplayPort FMC Daughter Card Revisions with the latest Bitec daughter card revision information.
- Added description for the AUX channel differential pair diagram and information about the AUX channel specification in the AUX Channel section.
- Added information about Bus LVDS I/O interface.
- Removed all information about the Intel FPGA HDMI interface to AN 837: Design Guidelines for Intel FPGA HDMI .
- Changed the title of this document to AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface.
- Added specific guidelines for Main Link RX and TX.
- Added information about receiver electrical parameters.
- Added guidelines for DisplayPort Power.
- Removed the schematic diagrams and provided links to the diagrams on the Bitec product page.