AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

Document Version Changes
2020.04.13
  • Updated the Main Link TX and Main Link RX sections to update the existing information and include information about Intel® Stratix® 10 L-tile and H-tile devices.
  • Updated the Implementing Bus LVDS I/O Interface section to include the latest I/O standard information.
  • Updated the Bitec DisplayPort FMC Daughter Card Revisions with the latest Bitec daughter card revision information.
2020.01.10
  • Added description for the AUX channel differential pair diagram and information about the AUX channel specification in the AUX Channel section.
  • Added information about Bus LVDS I/O interface.
2018.01.22
  • Removed all information about the Intel FPGA HDMI interface to AN 837: Design Guidelines for Intel FPGA HDMI .
  • Changed the title of this document to AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface.
  • Added specific guidelines for Main Link RX and TX.
  • Added information about receiver electrical parameters.
  • Added guidelines for DisplayPort Power.
  • Removed the schematic diagrams and provided links to the diagrams on the Bitec product page.
2015.11.02 Initial release.
Level Two Title