AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

ID 683623
Date 4/13/2020
Public Implementing Bidirectional LVDS

Alternatively, you can implement half-duplex, bidirectional LVDS using an external LVDS line driver/receiver.
Figure 5. External LVDS Line Driver/ReceiverThe figure shows an example of an external LVDS driver/receiver, TI SN65MLVD200A used in Bitec HSMC DisplayPort daughter card.

The interface to the device is straightforward. For example, TI SN65MLVD200A requires three LVTTL general purpose I/O pins (aux_oe, aux_out, aux_in). If the FPGA bank I/Os are not tolerant with LVTTL, a level shifter is required, as shown in the figure above.

There may be crosstalk from the single-ended LVTTL signals to the Main-Link high speed signals if the traces are routed close to each other. During board signal integrity (SI) design, pay special attention to routing.

Note: The DisplayPort Intel® FPGA IP design examples are developed based on the Bitec DisplayPort daughter card using TI SN65MLVD200A.

For more information about the BLVDS driver, TI SN65MLVD200A, refer to the SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet.