AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

ID 683623
Date 4/13/2020

1.1. DisplayPort Intel® FPGA IP Design Guidelines

The DisplayPort Intel® FPGA IP interface consists of a Main link, an auxiliary channel (AUX CH), and a Hot-Plug Detect (HPD) signal.
  • Main Link—Main Link is a unidirectional, high-bandwidth channel that transports video and audio over 1, 2, or 4 lanes at 8.1, 5.4, 2,7, and 1.62 Gigabits per second (Gbps) per lane. All lanes carry data. The clock is embedded in 8b/10b encoded serial data.
  • AUX CH—The AUX CH is 1 Megabits per second (Mbps) half-duplex bidirectional channel used for link management and device control.
  • HPD—The DisplayPort Intel® FPGA IP sink device uses HPD to detect its presence, The HPD signal serves as an interrupt request by the DisplayPort sink device.
Figure 1.  DisplayPort Intel® FPGA IP DisplayPort Transport ChannelsThis figure shows the DisplayPort Intel® FPGA IP link between a source and a sink device.

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