AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.1.2. Main Link TX Electrical Specifications

Use the listed Main Link transmitter electrical parameters for reference. Refer to the VESA DisplayPort Standard for other transmitter electrical parameters.
Table 5.  TP2 (TX External Connector)
Note: The Lane-to-Lane Output Skew specification at TP2 in VESA DisplayPort Standard version 1.2a differs from version 1.4.
Parameter Minimum Typical Maximum Notes
Maximum Output Voltage Level – – 1.38 V

Maximum differential peak-to-peak swing for all output level and pre-emphasis combinations

Lane-to-Lane Output Skew – – 1250 ps

VESA DisplayPort Standard version 1.4 for all data rates

Lane-to-Lane Output Skew (HBR, RBR) – – 2 UI

VESA DisplayPort Standard version 1.2a for HBR and RBR

Lane-to-Lane Output Skew (HBR2) – – 4 UI + 500 ps

VESA DisplayPort Standard version 1.2a for HBR2

Table 6.  TP3_EQ (Compliance Cable Model with Reference Receiver Equalizer)
Parameter Minimum Typical Maximum Notes
Maximum TX Total Jitter – – 0.65 UI

For HBR3, TPS4 pattern, at 1E-9
– – 0.62 UI

For HBR2, CP2520 pattern, at 1E-9
– – 0.40 UI

For HBR2, D10.2 pattern, at 1E-9
TX Differential Peak-to-Peak EYE Voltage at HBR3 75 mV – –

For HBR3, TPS4 pattern, at 1E-9
TX Differential Peak-to-Peak EYE Voltage at HBR2 90 mV – –

For HBR2, CP2520 pattern, at 1E-9
Note: For more information about TP2 and TP3_EQ compliance measurement points and reference receiver equalizer, refer to the VESA DisplayPort Standard.
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