AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

ID 683623
Date 4/13/2020
Public Detection of DisplayPort Upstream Source Device

The DisplayPort sink device senses the AUX+ and AUX- signal logic level to detect the upstream source.

The weak pull-up and pull-down resistors form a voltage divider that allows the sink device to detect the presence of the upstream source device.

Between the AC-coupling capacitor and the DisplayPort connector:

  • The source device weakly pulls down the AUX+ line to GND and weakly pulls up the AUX- line to DP_PWR (typically 3.3 V) with nominal 100K ohm resistors.
  • The sink device weakly pulls up the AUX+ line to 3.3 V and weakly pulls down the AUX- line to GND with nominal 1M ohm resistors.

The AUX+ and AUX- lines connect to the FPGA through 10K ohm resistors (e.g. RX_SENSE_P and RX_SENSE_N signals in the Bitec DisplayPort daughter card). The DisplayPort Intel® FPGA IP sink senses the logic level of the AUX+ and AUX- lines using the rx_cable_detect and rx_pwr_detect inputs and triggers the HPD signal when the powered upstream source device is detected.

The sense signals require level translation if they are connected to an FPGA I/O that is not 3.3V tolerant, for example, Intel® Arria® 10 device bank with VCCIO = 1.8 V.