AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

ID 683623
Date 4/13/2020
Public Implementing Bus LVDS I/O Interface

Intel devices offer on-chip Bus LVDS (BLVDS) I/O interface that you can use to implement the DisplayPort AUX channel.

The BLVDS I/O is a bidirectional differential I/O interface and requires special pin assignment consideration. Depending on the FPGA bank VCCIO voltage and I/O standard used, the BLVDS I/O may require a series resistor, Rs. The series resistor ensures the AUX channel differential voltage swing is below the maximum peak-to-peak voltage swing specification.

Figure 4. AUX Channel Using BLVDS I/O InterfaceThe figure shows the FPGA BLVDS I/O with series resistors for the DisplayPort Source (or Sink) AUX channel implementation.
Table 11.  BLVDS I/O SupportThe table lists the FPGA BLVDS I/O supported features and I/O standards.
Note: Vbias_TX (or Vbias_RX) = VCCIO/2, VCCIO is the FPGA I/O supply voltage.
FPGA Device Pin I/O Standard VCCIO Series Resistor (Rs) Value
Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 LVDS Differential SSTL-18 Class I 1.8 V 22 Ω
Differential SSTL-18 Class II
Arria V, Cyclone V, and Stratix V DIFFIO_RX 6 Differential SSTL-2 Class II 2.5 V 100 Ω
6 DFFIO_TX pins do not support true LVDS differential inputs.