AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.2.1. Implementing Bus LVDS I/O Interface

Intel devices offer on-chip Bus LVDS (BLVDS) I/O interface that you can use to implement the DisplayPort AUX channel.

The BLVDS I/O is a bidirectional differential I/O interface and requires special pin assignment consideration. Depending on the FPGA bank VCCIO voltage and I/O standard used, the BLVDS I/O may require a series resistor, Rs. The series resistor ensures the AUX channel differential voltage swing is below the maximum peak-to-peak voltage swing specification.

Figure 4. AUX Channel Using BLVDS I/O InterfaceThe figure shows the FPGA BLVDS I/O with series resistors for the DisplayPort Source (or Sink) AUX channel implementation.
Table 11.  BLVDS I/O SupportThe table lists the FPGA BLVDS I/O supported features and I/O standards.
Note: Vbias_TX (or Vbias_RX) = VCCIO/2, VCCIO is the FPGA I/O supply voltage.
FPGA Device Pin I/O Standard VCCIO Series Resistor (Rs) Value
Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 LVDS Differential SSTL-18 Class I 1.8 V 22 Ω
Differential SSTL-18 Class II
Arria V, Cyclone V, and Stratix V DIFFIO_RX 6 Differential SSTL-2 Class II 2.5 V 100 Ω
6 DFFIO_TX pins do not support true LVDS differential inputs.
Level Two Title