AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

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ID 683623
Date 4/13/2020
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface 2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface x
1.1. DisplayPort Intel® FPGA IP Design Guidelines
1.1. DisplayPort Intel® FPGA IP Design Guidelines x
1.1.1. Main Link 1.1.2. AUX Channel 1.1.3. DisplayPort Hot Plug Detect (HPD) 1.1.4. DisplayPort Power 1.1.5. Bitec DisplayPort Daughter Card Revisions
1.1.1. Main Link x
1.1.1.1. Main Link TX 1.1.1.2. Main Link TX Electrical Specifications 1.1.1.3. Main Link RX 1.1.1.4. Main Link RX Electrical Specifications
1.1.2. AUX Channel x
1.1.2.1. Implementing Bus LVDS I/O Interface 1.1.2.2. Implementing Bidirectional LVDS 1.1.2.3. Detection of DisplayPort Upstream Source Device
1. Design Guidelines for DisplayPort Intel® FPGA IP Interface
2. Document Revision History for AN 745: Design Guidelines for DisplayPort Intel® FPGA IP Interface

1.1.1.4. Main Link RX Electrical Specifications

Use the listed Main Link receiver electrical parameters for reference. Refer to the VESA DisplayPort Standard for other receiver electrical parameters.
Table 9.  TP3_EQ
Parameter Minimum Typical Maximum Notes
Minimum Receiver EYE Width at HBR3 0.35 UI – –

For HBR3, TPS4 pattern
RX Differential Peak-to-Peak EYE Voltage at HBR3 75 mV – –
Minimum Receiver EYE Width at HBR2 0.38 UI – –

For HBR2, CP2520 pattern
RX Differential Peak-to-Peak EYE Voltage at HBR2 70 mV – –
Note: For more information about TP3_EQ compliance measurement point and reference receiver equalizer, refer to the VESA DisplayPort Standard.
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