CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

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3.19.5. RS-FEC Interface

This interface is available when you generate IP core variation for Intel® Stratix® 10 device with 24.3 Gbps CPRI line bit rate.
Table 44.  RS-FEC Interface Signals
Signal Name Direction Description
fec_align_status Output Indicates alignment of the data in the RS-FEC block.
fec_syn_restarted Output Indicates when data in RS-FEC block is not aligned.
fec_corrected_cw_inc Output Asserts high when FEC corrects the error detected.
fec_uncorrected_cw_inc Output Asserts high when FEC detects an uncorrectable error.
fec_restart_sync Input Synchronous active-high reset signal for RS-FEC. You can use this signal only when fec_mode is high, which do not support for CPRI FEC mode. Drive this signal low for not using.
fec_bypass_error_correction Input Synchronous active-high signal to bypass only RS-FEC block.
fec_bypass Input Synchronous active-high signal to bypass RS-FEC block and PN-5280 scrambler/descrambler.
fec_parallellpbken Input When this signal is logic high, the internal logic skips PMA and performs a parallel loopback after RS-FEC.
lat_bitslip [21:0] Output Indicates latency introduced by RX bitslip logic in soft PCS.