CPRI Intel® FPGA IP User Guide

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ID 683595
Date 7/01/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

3.13. Media Independent Interface (MII) to External Ethernet Block

The media independent interface (MII) allows the CPRI Intel® FPGA IP to communicate directly with an external Ethernet MAC block. If you set the value of the Ethernet PCS interface parameter in the CPRI parameter editor to MII, your IP core includes this interface.

CPRI Intel® FPGA IP core contains the logic for Ethernet PCS block. This block does 4B/5B encoding to the received data through TX interface before sending it to the CPRI link. Likewise, it does 5B/4B decoding after receiving data from CPRI link before sending it back to RX interface. The available interface is intended to be connected to an external Ethernet MAC block. The external Ethernet MAC block should format the data following the IEEE 802.3 before sending the data to CPRI Intel® FPGA IP core (data from the Preamble to FCS). However, the IP observe all the incoming/outgoing data through this interface as raw data and apply the encoding/decoding respectively.

The MII supports the bandwidth described in Table 12 of the CPRI Specification, Achievable Ethernet bit rates.

The inter-packet gap should be 96 bits. Since, the data interface is 4-bit wide, the inter-packet gap corresponds to 24 mii_txclk cycles.

Table 32.  MII Signals

These signals are available if you set the value of the Ethernet PCS interface parameter in the CPRI parameter editor to MII. You can connect a user-defined Ethernet MAC to this interface.

The interface is fully compliant to the IEEE 802.3 100BASE-X 100Mbps MII specification. An Ethernet PCS block in the CPRI IP ensures the interface bandwidth matches the current CPRI line bit rate and accesses data at the correct CPRI frame positions according to the Z.194.0 pointer value.

You must monitor the MII FIFO status signals and ensure you do not overflow or underflow the FIFO.

The interface signals are clocked by the mii_rxclk or mii_txclk clock.

RX MII Signals

Signal Name

Direction

Description

mii_rxclk Input Clocks the MII receiver interface. You must drive this clock at the frequency of 25 MHz to achieve the 100 Mbps bandwidth required for this interface.
mii_rxreset_n Input Resets the MII receiver interface and FIFO read logic. This reset signal is active low.
mii_rxdv Output Ethernet receive data valid. Indicates the presence of valid data or initial K nibble on mii_rxd[3:0]. Each pulse of this signal is considered as one Ethernet packet.
mii_rxer Output Ethernet receive error. Indicates an error in the current nibble of mii_rxd. This signal is de-asserted at reset, and remains de-asserted while the CPRI IP is resetting and until link initialization completes.
mii_rxd[3:0] Output Ethernet receive nibble data. Data bus for data from the CPRI IP to the external Ethernet block. All bits are de-asserted during reset, and all bits are asserted after reset until the CPRI IP achieves frame synchronization.
TX MII Signals

Signal Name

Direction

Description

mii_txclk Input Clocks the MII transmitter interface. You must drive this clock at the frequency of 25 MHz to achieve the 100 Mbps bandwidth required for this interface.
mii_txreset_n Input Resets the MII transmitter interface and FIFO write logic. This signal is active low.
mii_txen Input Valid signal from the external Ethernet block, indicating the presence of valid data on mii_txd[3:0]. The external Ethernet block must also assert this signal two cycles before initial valid data, while the IP core inserts /J/ and /K/ nibbles in the data stream to form the start-of-packet symbol. Each pulse of this signal is considered as one Ethernet packet.
mii_txer Input Ethernet transmit coding error. When this signal is asserted, the CPRI IP core inserts an Ethernet HALT symbol in the data it passes to the CPRI link.
mii_txd[3:0] Input Ethernet transmit nibble data. The data transmitted from the external Ethernet block to the CPRI IP core, for transmission on the CPRI link. This input bus is synchronous to the rising edge of the mii_txclk clock.
MII Status Signals

Signal Name

Direction

Description

mii_tx_fifo_status[3:0] Output Ethernet Tx PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3]: Empty
  • Bit [2]: Almost empty
  • Bit [1]: Full
  • Bit [0]: Almost full

Almost Empty = FIFO level is 6.25% of maximum

Almost Full = FIFO level is 93.75% of maximum

When this signal value is 4'b0000, it could mean that the FIFO level is in between the levels. For example, it could be between Almost Empty and Almost Full.
Note: This status signal is delayed due to the internal CDC (clock domain crossing) between mii_txclk and cpri_clkout. Be cautious if Almost Full is reached while transmitting as the real-time level of the FIFO can be more than 93.75%. You are advised to plan your transmission so that you do not have to split the packets. For example:
  • Use smaller size packets
  • Increase the interpacket-gap corresponding to the packet size
  • Increase the size of FIFO depth by configuring the GUI parameter
mii_rx_fifo_status[3:0] Output Ethernet Rx PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3]: Empty
  • Bit [2]: Almost empty
  • Bit [1]: Full
  • Bit [0]: Almost full

Almost Empty = FIFO level is 6.25% of maximum

Almost Full = FIFO level is 93.75% of maximum

When this signal value is 4'b0000, it could mean that the FIFO level is in between the levels. For example, it could be between Almost Empty and Almost Full.

Figure 48. RX MII Timing Diagram


Figure 49. TX MII Timing Diagram


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