CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

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2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks

If you turn on Enable single-trip delay calibration in the CPRI parameter editor, and Synchronization mode is set to Slave, the CPRI Intel® FPGA IP core requires that you connect the IOPLL (pll_core block) and the Dynamic Phase Control Unit (DPCU) (pll_dpcu block). You must generate a device core PLL to create the IOPLL. Intel® provides the DPCU block with the CPRI IP, but you must connect it, and the IOPLL, in your design. A single IOPLL block and a single DPCU block can connect to multiple CPRI IP cores.

Figure 8. Connecting a Single DPCU Block and Single IOPLL Block to Multiple CPRI Intel® FPGA IP Cores

You must generate a non-transceiver PLL IP core to create the IOPLL block. You can use the IP Catalog to generate the external PLL IP core that configures a core PLL on the device. In the IP Catalog, select an IP core that configures an appropriate PLL on your target device.

For your Intel® Arria® 10 design, you must select Arria 10 FPLL in the IP Catalog.

In the parameter editor for the fPLL IP core, you must set the following parameter values:

  • Set fPLL Mode to Core.
  • Set the PLL output frequency to the expected input frequency for the CPRI IP cpri_coreclk input signal.
  • Turn on Enable access to dynamic phase shift ports.

You must connect the IOPLL and DPCU signals to the CPRI IP core signals according to the following rules. Refer to Example CPRI Intel FPGA IP Core Clock Connections in Different Clocking Modes for an illustration of the clock connections.

Table 15.  Required Connections to and From IOPLL Block in CPRI Design With Single-Trip Delay Calibration
IOPLL Block Signal Connect to
cntsel (input) DPCU pll_cntsel output signal
num_phase_shifts (input) DPCU pll_num_phase_shifts output signal
outclk_0 (output) CPRI Intel® FPGA IP cpri_coreclk input clock signal
phase_done (output) DPCU pll_phase_done input signal
phase_en (input) DPCU pll_phase_en output signal
refclk (input) CPRI Intel® FPGA IP tx_clkout output signal or output from the off-chip clean-up PLL
rst (input) Drive with the inverse of the CPRI Intel® FPGA IP reset_n input signal
scanclk (input) DPCU pll_scanclk output signal
updn (input) DPCU pll_updn output signal
Table 16.  Required Connections to and From DPCU Block in CPRI Design With Single-Trip Delay Calibration
DPCU Block Signal Connect to
clk Drive in the frequency range of 100–150 MHz.
Note: Intel® recommends that you drive this DPCU input clock with the source for the reconfig_clk.
reset_n (input) CPRI IP reset_n input signal
csr_bit_rate (input) If you turned on Enable line bit rate auto-negotiation in the CPRI parameter editor, connect to the CPRI IP nego_bitrate_out[5:0] output signal.

If autorate negotiation is not turned on, hardwire the DPCU csr_bit_rate signal to the encoded value for the CPRI line bit rate:

  • 6'b000001: 0.6144 Gbps
  • 6'b000010: 1.2288 Gbps
  • 6'b000100: 2.4576 Gbps
  • 6'b000101: 3.0720 Gbps
  • 6'b001000: 4.9150 Gbps
  • 6'b001010: 6.1440 Gbps
  • 6'b010110: 8.11008 Gbps
  • 6'b010000: 9.8304 Gbps
  • 6'b010100: 10.1376 Gbps
  • 6b'011000: 12.16512 Gbps
  • 6'b110000 : 24.33024 Gbps
cal_status (output) CPRI IP cal_status input signal
cal_ctrl (input) CPRI IP cal_ctrl output signal
pll_cntsel (output) IOPLL cntsel input signal
pll_num_phase_shifts (output) IOPLL num_phase_shifts input signal
pll_phase_done (input) IOPLL phase_done output signal
pll_phase_en (output) IOPLL phase_en input signal
pll_scanclk (output) IOPLL scanclk input signal
pll_updn (output) IOPLL updn input signal

User logic must provide the connections. Refer to the Figure: CPRI Slave IP Core in External Clocking Mode with Single-Trip Delay Calibration Feature