CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.18.2. Delay Requirements

CPRI Specification requirements R-17, R-18, and R-18A address jitter and frequency accuracy in the RE core clock for radio transmission. The relevant clock synchronization is performed using an external clean-up PLL that is not included in the CPRI Intel® FPGA IP.

CPR v7.0 Specification requirement R-20A addresses the maximum allowed delay in switching between receiving and transmitting on the radio interface. The radio interface is implemented outside the IP core based on raw data presented on the AUX interface or other direct interfaces. Because the IP core provides duplex communication on these interfaces, no delay calculation is required.

Requirement R-19 specifies that the link delay accuracy for the downlink between the synchronization master SAP and the synchronization slave SAP, excluding the cable length, be within ±8.138 ns. Requirements R-20 and R-21 extrapolate this requirement to single-hop round-trip delay accuracy. R-20 requires that the accuracy of the round-trip delay, excluding cables, be within ±16.276 ns, and R-21 requires that the round-trip cable delay measurement accuracy be within the same range. Requirement R-21A extrapolates this requirement further, to multihop round-trip delay accuracy. In calculating these delays, Intel® assumes that the downlink and uplink cable delays have the same duration.

Figure 56. Single-Hop CPRI Intel® FPGA IP Configuration Delay Measurement Reference PointsThe round-trip cable delay is the sum of the T12 and T34 delays. The two delays are assumed to have the same duration.
Figure 57. Multihop CPRI Intel® FPGA IP Configuration Delay Measurement Reference PointsThe duration of TBdelay depends on your routing layer implementation.