CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.12. L1 Debug Interface

If you turn on Enable L1 debug interfaces in the CPRI parameter editor, the L1 debug interface is available.

Table 31.  Direct L1 Control and Status Interface SignalsAll of the L1 debug signals are asynchronous.

Signal Name



rx_lcv Output Indicates the IP core has detected excessive 8B10B errors received.

The IP core asserts this signal when it detects more than 15 bits of error.

rx_freq_alarm Output Indicates the CPRI receive clock (receiver CDR recovered clock) and the main IP core clock (cpri_clkout) have a PPM difference. The IP core asserts this alarm each time it detects a mismatch.