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2.1. Installation and Licensing
2.2. Generating CPRI Intel® FPGA IP Core
2.3. CPRI Intel® FPGA IP File Structure
2.4. CPRI Intel® FPGA IP Core Parameters
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks
2.6. Simulating Intel FPGA IP Cores
2.7. Understanding the Testbench
2.8. Running the Design Example
2.9. Compiling the Full Design and Programming the FPGA
2.5.1. Adding the Transceiver TX PLL IP Core
2.5.2. Adding the Reset Controller
2.5.3. Adding the Transceiver Reconfiguration Controller
2.5.4. Adding the Off-Chip Clean-Up PLL
2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks
2.5.6. Transceiver PLL Calibration
2.5.7. Reference and System PLL Clock for your IP Design
3.1. Interfaces Overview
3.2. CPRI Intel® FPGA IP Core Clocking Structure
3.3. CPRI Intel® FPGA IP Core Reset Requirements
3.4. Start-Up Sequence Following Reset
3.5. AUX Interface
3.6. Direct IQ Interface
3.7. Ctrl_AxC Interface
3.8. Direct Vendor Specific Access Interface
3.9. Real-Time Vendor Specific Interface
3.10. Direct HDLC Serial Interface
3.11. Direct L1 Control and Status Interface
3.12. L1 Debug Interface
3.13. Media Independent Interface (MII) to External Ethernet Block
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block
3.15. CPU Interface to CPRI Intel® FPGA IP Registers
3.16. Auto-Rate Negotiation
3.17. Extended Delay Measurement
3.18. Deterministic Latency and Delay Measurement and Calibration
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces
3.20. Testing Features
3.19.1. CPRI Link
3.19.2. Main Transceiver Clock and Reset Signals
3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface
3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface
3.19.5. RS-FEC Interface
3.19.6. Interface to the External Reset Controller
3.19.7. Interface to the External PLL
3.19.8. Transceiver Debug Interface
3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs
The CPRI Intel® FPGA IP uses a dedicated clock, latency_sclk, to measure the delay through the RX and TX Intel® Stratix® 10 device hard FIFOs that are configured in the CPRI IP core.
The delay calculation process is identical for the two directions of flow through the IP core; the XCVR_TX_FIFO_DELAY and XCVR_RX_FIFO_DELAY registers hold the same information for the two directions.
To measure the current Tx delay through the hard FIFOs:
- Check the tx_pcs_fifo_delay_valid and tx_core_fifo_delay_valid fields of the XCVR_TX_FIFO_DELAY register at offset 0x84 to ensure the delay count values are updated.
- Add the delay count values in the tx_pcs_fifo_delay and tx_core_fifo_delay fields of the XCVR_TX_FIFO_DELAY register at offset 0x84.
- Multiply the result by the clock period of the latency_sclk.
- Divide this result by 128.
To measure the current Rx delay through the hard FIFOs:
- Check the rx_pcs_fifo_delay_valid and rx_core_fifo_delay_valid fields of the XCVR_RX_FIFO_DELAY register at offset 0x88 to ensure the delay count values are updated.
- Add the delay count values in the rx_pcs_fifo_delay and rx_core_fifo_delay fields of the XCVR_RX_FIFO_DELAY register at offset 0x88.
- Multiply the result by the clock period of the latency_sclk.
- Divide this result by 128.
Figure 55. Additional Delay Through Intel Stratix 10 Hard FIFOs